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How to program both of FPGA bit file and SW binary code into SPI serial flash ?

Status: Open.

#79 In chipsalliance/VeeRwolf;

· kidonglee opened on Aug 25, 2025

VeeRwolf build issue

Status: Open.

#78 In chipsalliance/VeeRwolf;

· sabari-vvdn opened on Jun 24, 2025

Error in Build of Predefined examples of Zephyr

Status: Open.

#69 In chipsalliance/VeeRwolf;

· ayusdixit opened on Jan 31, 2024

May I ask how to generate the build. h file used for FPGA project？

Status: Open.

#68 In chipsalliance/VeeRwolf;

· yaanng2022 opened on Nov 27, 2023

Assertion error when running fusesoc simulation

Status: Open.

#67 In chipsalliance/VeeRwolf;

· MoonisAmir10 opened on Aug 29, 2023

Error when building Zephyr example

Status: Open.

#63 In chipsalliance/VeeRwolf;

· aleksaj-vtool opened on Jan 30, 2023

Read access stops when read/write access is repeated

Status: Open.

#59 In chipsalliance/VeeRwolf;

· yafuru0 opened on Dec 26, 2022

Tested/Implemented on other cores

Status: Open.

#58 In chipsalliance/VeeRwolf;

· geoalx opened on Dec 3, 2022

axi/wb bus cycle times

Status: Open.

#55 In chipsalliance/VeeRwolf;

· jamesbbecker opened on Jun 27, 2022

fusesoc run --target=basys3 with vivado 2021.2

Status: Open.

#51 In chipsalliance/VeeRwolf;

· kendallgreen opened on Nov 16, 2021

[Nexys4 DDR] Struggling to load into ICCM (address 0xEE000000)

Status: Open.

#46 In chipsalliance/VeeRwolf;

· mablinov opened on Oct 13, 2021

ERROR: [Labtools 27-3165] End of startup status: LOW when [ run --target=nexys_a7 --flag=cpu_el2 swervolf]

Status: Open.

#43 In chipsalliance/VeeRwolf;

· nicolast0604 opened on Sep 23, 2021