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Resolve "Rejected valid signal name" #2102

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Resolve "Rejected valid signal name" #2102

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f287035
ML fixed #2076
Feb 6, 2024
72ff5ce
ML added testcase for #2076
Feb 6, 2024
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2 changes: 2 additions & 0 deletions verilog/parser/verilog.y
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Original file line number Diff line number Diff line change
Expand Up @@ -773,6 +773,8 @@ KeywordIdentifier
{ $$ = std::move($1); }
| TK_discrete
{ $$ = std::move($1); }
| TK_analog
{ $$ = std::move($1); }
/* TK_sample is in SystemVerilog coverage_event */
| TK_sample
{ $$ = std::move($1); }
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1 change: 1 addition & 0 deletions verilog/parser/verilog_parser_unittest.cc
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Expand Up @@ -1773,6 +1773,7 @@ static constexpr ParserTestCaseArray kModuleTests = {
// keyword tests
"module keyword_identifiers;\n"
"reg branch; // branch is a Verilog-AMS keyword\n"
"reg analog; // analog is a Verilog-AMS keyword\n"
"input from; // from is a Verilog-AMS keyword\n"
"wire access; // access is a Verilog-AMS keyword\n"
"wire exclude; // exclude is a Verilog-AMS keyword\n"
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