Support MilkV Titan and Backport PCIe, PLIC driver

[WangJia-UR]

1. Backport subject "PCI: Silence set affinity failed warning"
2. Backport PLIC driver to support plic driver early
3. Add MilkV-Titan support.

Summary by Sourcery

Add MilkV Titan platform support and enhance RISC-V interrupt/PCIe handling, while cleaning up MSI affinity handling across multiple PCI host controllers.

New Features:

• Support UltraRISC DP1000 Titan board via new device trees and pinctrl configuration.
• Enable early initialization of the RISC-V PLIC for compatible SoCs using fwnode-based probing.
• Add RISC-V interrupt controller handling for AIA-style local interrupts and extended interrupt masking on 32-bit systems.
• Preserve and restore MSI interrupt masks across suspend/resume for the UltraRISC DesignWare PCIe host controller.

Bug Fixes:

• Fix PLIC enable register access races by using IRQ-safe spin locking in interrupt enable/disable paths and suspend/resume.
• Correct RISC-V local interrupt masking to handle high interrupt IDs via IEH on 32-bit systems.
• Fix irq matrix sizing by dynamically allocating per-CPU and global bitmaps instead of relying on architecture-specific IRQ_MATRIX_BITS.
• Avoid spurious warnings and unsupported operations from PCI/MSI irq_set_affinity by marking domains that do not support affinity steering and dropping dead set_affinity implementations.
• Make UltraRISC pinctrl configuration robust by deriving port/pin from pin numbers and properly translating generic pinconf options into hardware bias settings.

Enhancements:

• Refactor the RISC-V PLIC driver to be fwnode-centric, improve error reporting with fwnode tags, and centralize parsing of contexts and parent interrupts.
• Improve RISC-V core interrupt mapping logs to reflect AIA-capable systems and report custom local interrupts more clearly.
• Tighten UltraRISC pinctrl and DT bindings, including updated pinmux/bias macros and debugging output, and track port metadata via match data.

[sourcery-ai]

Reviewer's Guide

Backports and extends the RISC‑V interrupt and PCIe stack to support early PLIC init and MilkV Titan/UltraRISC DP1000 platforms, reworking irq matrix allocation, disabling MSI affinity steering for several host controllers, enhancing the UltraRISC pinctrl driver and DT bindings, and wiring up new DTS variants for the Titan board.

Sequence diagram for RISC‑V external interrupt handling via intc and PLIC

sequenceDiagram
    participant CPU
    participant riscv_intc as riscv_intc_irq
    participant riscv_intc_aia as riscv_intc_aia_irq
    participant intc_domain
    participant PLIC as plic_handle_irq
    participant plic_domain

    rect rgb(235,235,255)
        CPU->>riscv_intc: external interrupt entry
        alt AIA available (SxAIA)
            riscv_intc->>riscv_intc_aia: call when topi support present
            loop while CSR_TOPI nonzero
                riscv_intc_aia->>intc_domain: generic_handle_domain_irq(topi >> TOPI_IID_SHIFT)
            end
        else legacy
            riscv_intc->>intc_domain: generic_handle_domain_irq(cause)
        end
    end

    rect rgb(235,255,235)
        intc_domain->>PLIC: PLIC parent irq raised (RV_IRQ_EXT)
        activate PLIC
        PLIC->>PLIC: plic_get_hwirq() in loop
        loop while hwirq != 0
            PLIC->>plic_domain: generic_handle_domain_irq(hwirq)
            alt mapping not found
                PLIC->>PLIC: pr_warn_ratelimited(fwnode, hwirq)
            end
        end
        deactivate PLIC
    end

Loading

Sequence diagram for UltraRISC PCIe MSI mask save/restore on suspend/resume

sequenceDiagram
    participant PM as PM_core
    participant pdev as platform_device
    participant upcie as ultrarisc_pcie
    participant dw as dw_pcie
    participant pp as dw_pcie_rp

    rect rgb(235,235,255)
        PM->>pdev: suspend callback
        pdev->>upcie: ultrarisc_pcie_suspend(state)
        upcie->>dw: get pci = ultrarisc_pcie->pci
        dw->>pp: get pp = &pci->pp
        upcie->>pp: num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL
        upcie->>pp: raw_spin_lock_irqsave(pp->lock)
        loop for each ctrl
            upcie->>upcie: irq_mask[ctrl] = pp->irq_mask[ctrl]
        end
        upcie->>pp: raw_spin_unlock_irqrestore(pp->lock)
        upcie-->>pdev: return 0
    end

    rect rgb(235,255,235)
        PM->>pdev: resume callback
        pdev->>upcie: ultrarisc_pcie_resume()
        upcie->>dw: get pci = ultrarisc_pcie->pci
        dw->>pp: get pp = &pci->pp
        upcie->>pp: num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL
        upcie->>pp: raw_spin_lock_irqsave(pp->lock)
        loop for each ctrl
            upcie->>pp: pp->irq_mask[ctrl] = ultrarisc_pcie->irq_mask[ctrl]
            upcie->>dw: dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + ctrl * MSI_REG_CTRL_BLOCK_SIZE, pp->irq_mask[ctrl])
        end
        upcie->>pp: raw_spin_unlock_irqrestore(pp->lock)
        upcie-->>pdev: return 0
    end

Loading

Class diagram for updated RISC‑V PLIC driver structures and probe flow

classDiagram
    class plic_priv {
        +struct fwnode_handle *fwnode
        +struct cpumask lmask
        +struct irq_domain *irqdomain
        +void __iomem *regs
        +unsigned long plic_quirks
        +u32 nr_irqs
        +unsigned long *prio_save
    }

    class plic_handler {
        +bool present
        +void __iomem *hart_base
        +void __iomem *enable_base
        +u32 *enable_save
        +raw_spinlock_t enable_lock
        +struct plic_priv *priv
    }

    class plic_probe {
        +int plic_probe(struct fwnode_handle *fwnode)
        +int plic_platform_probe(struct platform_device *pdev)
        +int plic_early_probe(struct device_node *node, struct device_node *parent)
    }

    class plic_helpers {
        +int plic_parse_nr_irqs_and_contexts(struct fwnode_handle *fwnode, u32 *nr_irqs, u32 *nr_contexts)
        +int plic_parse_context_parent(struct fwnode_handle *fwnode, u32 context, u32 *parent_hwirq, int *parent_cpu)
        +void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
        +int plic_irq_suspend(void)
        +void plic_irq_resume(void)
    }

    class plic_global_state {
        +int plic_parent_irq
        +bool plic_global_setup_done
        +struct plic_handler plic_handlers_per_cpu
    }

    class irqchip_registration {
        +struct platform_driver plic_driver
        +IRQCHIP_DECLARE(riscv, allwinner_sun20i_d1_plic, plic_early_probe)
        +IRQCHIP_DECLARE(ultrarisc_dp1000_plic, ultrarisc_dp1000_plic, plic_early_probe)
    }

    plic_handler --> plic_priv : priv
    plic_global_state --> plic_handler : manages per_cpu
    plic_probe --> plic_priv : allocates/initializes
    plic_probe --> plic_handler : initializes per_cpu handlers
    plic_probe --> plic_helpers : uses
    plic_helpers --> plic_priv : reads nr_irqs, regs
    plic_helpers --> plic_handler : toggles enable bits
    plic_global_state --> irqchip_registration : uses parent_irq mapping
    irqchip_registration --> plic_probe : calls from probe/early_probe

Loading

Class diagram for irq_matrix and cpumap rework

classDiagram
    class cpumap {
        +unsigned int available
        +unsigned int allocated
        +unsigned int managed
        +unsigned int managed_allocated
        +bool initialized
        +bool online
        +unsigned long *managed_map
        +unsigned long alloc_map[]
    }

    class irq_matrix {
        +raw_spinlock_t lock
        +unsigned int alloc_start
        +unsigned int alloc_end
        +unsigned int alloc_size
        +unsigned int matrix_bits
        +unsigned int total_allocated
        +unsigned int online_maps
        +struct cpumap __percpu *maps
        +unsigned long *system_map
        +unsigned long scratch_map[]
        +struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, unsigned int alloc_start, unsigned int alloc_end)
    }

    irq_matrix --> cpumap : maps~per_cpu~

Loading

Class diagram for UltraRISC DP1000 pinctrl structures and helpers

classDiagram
    class ur_port_desc {
        +const char *name
        +u32 npins
        +u32 mux_offset
        +u32 conf_offset
    }

    class ur_pinctrl_match_data {
        +const struct pinctrl_pin_desc *pins
        +u32 npins
        +u32 offset
        +u32 num_ports
        +struct ur_port_desc ports[]
    }

    class ur_pin_val {
        +u32 port
        +u32 pin
        +u32 conf
    }

    class ur_pinctrl {
        +struct device *dev
        +void __iomem *base
        +struct pinctrl_desc *pctl_desc
        +struct pinctrl_dev *pctl_dev
        +const struct ur_pinctrl_match_data *match_data
        +raw_spinlock_t lock
        +struct mutex mutex
    }

    class ur_pinctrl_helpers {
        +int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, struct ur_pin_val *pin_val, u32 pin_num)
        +int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals, unsigned long *config)
        +int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals)
        +int ur_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs)
        +int ur_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)
        +int ur_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned int selector, unsigned long *config)
    }

    ur_pinctrl --> ur_pinctrl_match_data : match_data
    ur_pinctrl_match_data --> ur_port_desc : ports
    ur_pinctrl_helpers --> ur_pinctrl : operates_on
    ur_pinctrl_helpers --> ur_pinctrl_match_data : scans ports
    ur_pinctrl_helpers --> ur_pin_val : builds_and_programs

Loading

File-Level Changes

Change	Details	Files
Refactor RISC-V PLIC driver to be fwnode-based, support early-IRQCHIP probing, and improve locking and logging semantics.	Change plic_priv to store an fwnode_handle instead of struct device and use it for logging and IRQ domain lookup. Convert enable_lock users to raw_spin_lock_irqsave/irqrestore in the main toggle and suspend/resume paths. Factor out helpers to parse PLIC IRQ counts and per-context parent info from fwnode/OF and use them in a rewritten plic_probe taking an fwnode_handle. Delay creation of the irqdomain until after contexts/handlers are discovered, add proper cleanup paths for partial setup failures, and only do global cpuhp/syscore/parent-IRQ setup once all online handlers are present. Add a platform wrapper probe, an early IRQCHIP_DECLARE-based probe for specific compatibles, adjust pr_fmt and log messages to include %pfwP, and update driver registration metadata.	drivers/irqchip/irq-sifive-plic.c
Enhance RISC-V local interrupt controller to support AIA and 32-bit extended interrupt enables, and improve init reporting.	Add AIA-specific interrupt handler that services CSR_TOPI in a loop and call into generic_handle_domain_irq. Extend irq_mask/unmask to use CSR_IEH for hwirq >= BITS_PER_LONG on 32-bit builds. Adjust init common path to log 64 mapped local interrupts when the SxAIA ISA extension is present and simplify printk formatting. Include asm/hwcap.h for ISA extension checks.	drivers/irqchip/irq-riscv-intc.c
Rework irq matrix and IRQ_MATRIX_BITS handling to support variable-width matrices and decouple from NR_VECTORS.	Make struct cpumap and irq_matrix store their bitmaps as flexible arrays and pointers rather than fixed-size arrays, and allocate enough space dynamically based on matrix_bits. Allocate per-CPU cpumap structures with room for both alloc_map and managed_map bitmaps and wire managed_map to the second half of the allocation. Remove the global IRQ_MATRIX_BITS define from x86 hw_irq.h and the associated fixed-size arrays in irq/matrix.c.	kernel/irq/matrix.c arch/x86/include/asm/hw_irq.h
Disable MSI IRQ affinity steering for a broad set of PCIe/MSI host controllers using a new MSI_FLAG_NO_AFFINITY flag and by removing custom irq_set_affinity stubs.	Introduce MSI_FLAG_NO_AFFINITY and shift MSI_FLAG_PCI_IMS to the next bit in include/linux/msi.h, and adjust the default chip-op wiring in kernel/irq/msi.c so msi_domain_set_affinity is only installed when NO_AFFINITY is clear. Update multiple PCIe host controller MSI domain_info instances (DesignWare, Mediatek, VMD, Mobiveil, Altera, Broadcom STB, Xilinx NWL, Aardvark, Tegra, R-Car, Xilinx) to set MSI_FLAG_NO_AFFINITY. Drop per-driver irq_set_affinity implementations or stubs from their MSI/INTx irq_chips, relying on the NO_AFFINITY behavior instead.	include/linux/msi.h kernel/irq/msi.c drivers/pci/controller/dwc/pcie-designware-host.c drivers/pci/controller/pcie-mediatek-gen3.c drivers/pci/controller/vmd.c drivers/pci/controller/mobiveil/pcie-mobiveil-host.c drivers/pci/controller/pcie-altera-msi.c drivers/pci/controller/pcie-brcmstb.c drivers/pci/controller/pcie-mediatek.c drivers/pci/controller/pcie-xilinx-nwl.c drivers/pci/controller/pci-aardvark.c drivers/pci/controller/pci-tegra.c drivers/pci/controller/pcie-rcar-host.c drivers/pci/controller/pcie-xilinx.c drivers/pci/controller/dwc/pci-keystone.c
Add power-management support for UltraRISC DesignWare PCIe host and plumb it into the platform driver.	Extend ultrarisc_pcie struct to store per-MSI-controller irq_mask snapshots. Implement ultrarisc_pcie_suspend to save pp->irq_mask[] under lock before suspend and ultrarisc_pcie_resume to restore them to software state and HW MSI mask registers. Register these as .suspend and .resume callbacks in the ultrarisc_pcie platform_driver.	drivers/pci/controller/dwc/pcie-ultrarisc.c
Improve UltraRISC DP1000 pinctrl driver, its match data, and DT bindings to support per-pin pinconf via standard pinconf enums instead of custom macros.	Add num_ports to ur_pinctrl_match_data and initialize it for DP1000, enabling iteration over port descriptors. Implement helpers to map a linear pin number to (port,pin) using the SoC port descriptors and to translate pinconf-generic configs into the driver’s ur_pin_val.conf bitfields. Refactor ur_pin_config_set to use these helpers and apply configuration per pin, with better debug messages and error handling for invalid configs. Adjust ur_set_pin_conf logging and minor allocations/cleanup patterns in the core driver for clarity; relax some unnecessary dev_err logging on alloc failure. Update the DT binding schema to describe pinctrl-pins and pinconf-pins as PORT/PIN/FUNC or PORT/PIN/BIAS triplets rather than macro-expanded values, and rename/normalize UltraRISC naming. Rework the ur-dp1000-pinctrl.h header to remove UR_DP1000_IOPAD and change UR_DP1000_BIAS to only encode pull/drive, matching the updated DT format.	drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h
Wire up new UltraRISC DP1000 "Titan" board support in the RISC-V device tree and enable its DTB build.	Add dp1000-titan-v1.dts and a Titan-specific pinctrl dtsi file, and convert the generic dp1000 .dts into a shared dp1000.dtsi include. Update the ultrarisc DT Makefile to build the new dp1000-titan-v1.dtb alongside existing EVB and MO variants and stop building the old monolithic dp1000.dtb. Introduce (or extend) board-specific pinctrl dtsi files for EVB and MO variants to align with the refactored base dp1000.dtsi layout (content not shown in diff).	arch/riscv/boot/dts/ultrarisc/Makefile arch/riscv/boot/dts/ultrarisc/dp1000.dtsi arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts

---

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[deepin-ci-robot]

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[Copilot]

Pull request overview

This pull request adds support for the MilkV Titan board and backports PCIe MSI affinity handling and PLIC driver improvements for the UltraRISC DP1000 platform.

• Introduces a new MSI_FLAG_NO_AFFINITY flag to handle PCI MSI controllers that don't support IRQ affinity steering
• Refactors IRQ matrix allocation to use dynamic sizing instead of architecture-specific constants
• Modernizes the RISC-V PLIC driver with fwnode support, improved locking, and early probe capability
• Adds pinctrl driver improvements with proper pin-to-port/pin conversion and generic pinconf handling
• Introduces device tree support for the MilkV Titan board

Reviewed changes

Copilot reviewed 33 out of 33 changed files in this pull request and generated 4 comments.

Show a summary per file

File	Description
kernel/irq/msi.c	Adds MSI_FLAG_NO_AFFINITY check to avoid setting affinity on unsupported controllers
kernel/irq/matrix.c	Refactors to use dynamic allocation with struct_size for flexible matrix sizing
include/linux/msi.h	Defines new MSI_FLAG_NO_AFFINITY flag and shifts MSI_FLAG_PCI_IMS
arch/x86/include/asm/hw_irq.h	Removes architecture-specific IRQ_MATRIX_BITS constant
drivers/pci/controller/*	Removes stub set_affinity implementations and adds MSI_FLAG_NO_AFFINITY across multiple controllers
drivers/pci/controller/dwc/pcie-ultrarisc.c	Adds suspend/resume support with MSI mask state preservation
drivers/irqchip/irq-sifive-plic.c	Major refactoring to use fwnode, improved error handling, IRQ-safe locking, and early probe support
drivers/irqchip/irq-riscv-intc.c	Adds AIA interrupt handling and IEH support for 32-bit systems with extended interrupts
drivers/pinctrl/ultrarisc/*	Refactors pinctrl driver with improved port/pin handling and generic pinconf translation
include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h	Updates pin configuration macros to remove port/pin from BIAS macro
arch/riscv/boot/dts/ultrarisc/*	Adds Titan board DTS, updates EVB/MO board pinctrl, moves pinmux to dp1000.dtsi
Documentation/devicetree/bindings/pinctrl/*	Updates binding documentation with new macro format

Comments suppressed due to low confidence (1)

drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c:514

• The variable declaration for 'struct resource *res' should appear at the beginning of the function block, not in the middle after an if statement. This violates C89/C90 standards and may cause compilation issues with certain compilers. Move line 514 to the top of the function with other variable declarations.

	ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL);
	if (!ur_pinctrl) {
		ret = -ENOMEM;
		goto free_pinctrl_desc;
	}
	struct resource *res;

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

[Copilot]

The loop variable 'i' is declared in the for loop initializer, which is a C99 feature. This may cause compilation issues with strict C89 compilers or certain kernel configurations. Declare 'i' at the beginning of the function instead.

[Copilot]

The loop variable 'i' is declared in the for loop initializer, which is a C99 feature. This may cause compilation issues with strict C89 compilers or certain kernel configurations. Declare 'i' at the beginning of the function instead.

[Copilot]

Potential division by zero: if pp->num_vectors is less than MAX_MSI_IRQS_PER_CTRL (32), num_ctrls will be 0, causing the loop to be skipped but potentially leading to unexpected behavior. Consider adding a validation check or using DIV_ROUND_UP to ensure proper handling of edge cases.

[Copilot]

Potential division by zero: if pp->num_vectors is less than MAX_MSI_IRQS_PER_CTRL (32), num_ctrls will be 0, causing the loop to be skipped but potentially leading to unexpected behavior. Consider adding a validation check or using DIV_ROUND_UP to ensure proper handling of edge cases.

[opsiff]

1.需要确认下以下fix是否需要
commit 678c607
Author: Anup Patel [email protected]
Date: Mon Feb 26 09:37:37 2024 +0530

irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA

Use riscv_intc_aia_irq() as the low-level interrupt handler instead of the
existing riscv_intc_irq() default handler to make demultiplexing work
correctly.

Also print "using AIA" in the INTC boot banner when AIA is available.

Fixes: 3c46fc5b5507 ("irqchip/riscv-intc: Add support for RISC-V AIA")
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

commit ca5b0b7
Author: Samuel Holland [email protected]
Date: Tue Mar 12 14:28:08 2024 -0700

irqchip/riscv-intc: Fix use of AIA interrupts 32-63 on riscv32

riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
check passes even though AIA provides 64 interrupts. Adjust the condition to
only check the custom range for interrupts outside the standard range, and
adjust the standard range when AIA is available.

Fixes: 3c46fc5b5507 ("irqchip/riscv-intc: Add support for RISC-V AIA")
Fixes: 678c607ecf8a ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

commit 6eabf65
Author: Charlie Jenkins [email protected]
Date: Tue Sep 3 16:36:19 2024 -0700

irqchip/sifive-plic: Return error code on failure

Set error to -ENOMEM if kcalloc() fails or if irq_domain_add_linear()
fails inside of plic_probe() instead of returning 0.

Fixes: 4d936f10ff80 ("irqchip/sifive-plic: Probe plic driver early for Allwinner D1 platform")
Reported-by: kernel test robot <[email protected]>
Reported-by: Dan Carpenter <[email protected]>
Signed-off-by: Charlie Jenkins <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/all/20240903-correct_error_codes_sifive_plic-v1-1-d929b79663a2@rivosinc.com
Closes: https://lore.kernel.org/r/[email protected]/

2. series 标题PCI: xxx : Silence 'set affinity failed' warning缺' '以及有缺失需要确认下下面补丁是否需要
   PCI: plda: Silence 'set affinity failed' warning

[WangJia-UR]

commit 678c607

1. 三个commit： 678c607, ca5b0b7, 6eabf65 已加入PR。
2. commit msg丢失''问题已修复，6.6版本没有plda驱动，暂不需要合入对应的patch。

[deepin-ci-robot]

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This pull-request has been approved by: opsiff

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