Support corepvt, phy leds on titan and update dts

[WangJia-UR]

1. Backport the ultrarisc dp1000 plic implementation from the upstream;
2. Support corepvt of ultrarisc dp100;
3. Backport ledtrig-netdev and "net: phy: realtek: Add support for PHY LEDs on RTL8211F" to enable setting phy leds on MilkV Titan;
4. Update ultrarisc device tree and defconfig.

Summary by Sourcery

Add UltraRISC DP1000 core PVT hwmon support, enhance LED trigger and Realtek PHY LED integration, and update UltraRISC platform IRQ, PCIe, and device tree bindings for DP1000/Titan.

New Features:

• Introduce a hwmon driver and DT binding for the UltraRISC DP1000 core PVT voltage and temperature sensor.
• Enable hardware-controlled PHY LEDs on Realtek RTL8211F PHYs and advertise the netdev LED trigger via a module alias.
• Extend netdev LED triggers to support additional link speeds up to 10G and expose only speeds supported by the underlying link.

Bug Fixes:

• Handle the UltraRISC CP100 PLIC claim register erratum by isolating pending interrupts before claiming and restoring the enable state.
• Avoid spurious error logs when LED backends do not support fixed brightness settings or are unplugged, and correctly apply default and panic LED triggers.

Enhancements:

• Refine LED trigger core to support a "default" trigger selection via sysfs and deferred loading of default trigger modules.
• Improve netdev LED trigger behavior with hardware-offload awareness, cached link mode capabilities, and updated sysfs visibility semantics.
• Adjust PCIe and PLIC UltraRISC compatibles and DT bindings to match upstream names and add the CP100 PLIC compatible pairing.
• Clarify UltraRISC DP1000 pinctrl binding header naming in documentation and correct the DP1000 M0 DTB name in the UltraRISC DTS Makefile.

Build:

• Hook the new UltraRISC core PVT hwmon driver into the hwmon Kconfig and Makefile so it can be built when enabled.

Documentation:

• Document the UltraRISC DP1000 core PVT device tree binding for the new hwmon driver.
• Update PLIC and pinctrl device tree binding documentation to reflect new UltraRISC compatibles and header names.

[sourcery-ai]

Reviewer's Guide

Backports and extends PLIC, LED trigger, and Realtek PHY LED support while adding an UltraRISC DP1000 core PVT hwmon driver and updating Ultrarisc DTS/defconfig so MilkV Titan can use PHY-controlled LEDs and on-chip sensors correctly.

Sequence diagram for cp100 PLIC interrupt handling with claim-register erratum

sequenceDiagram
    participant Device as Device_irq_source
    participant PLIC as cp100_PLIC
    participant CPU as RISC_V_CPU
    participant Handler as plic_handle_irq_cp100
    participant Core as cp100_get_hwirq
    participant IRQ as generic_handle_domain_irq

    Device->>PLIC: Assert_interrupt
    PLIC-->>CPU: External_interrupt
    CPU->>Handler: Enter_chained_handler
    Handler->>Core: cp100_get_hwirq(handler, claim)
    loop While_pending_irq
        Core->>Core: cp100_isolate_pending_irq()
        Core->>PLIC: Read_pending_registers
        Core->>PLIC: Write_enable_registers_isolating_first_pending
        Core->>PLIC: Read_claim_register
        Core-->>Handler: hwirq
        Handler->>IRQ: generic_handle_domain_irq(irqdomain, hwirq)
        IRQ-->>Handler: err
        alt Mapping_missing
            Handler->>Handler: pr_warn_ratelimited()
        end
        Core->>PLIC: Restore_enable_registers_from_enable_save
    end
    Handler->>CPU: chained_irq_exit()
    CPU-->>PLIC: End_of_interrupt

Loading

Sequence diagram for LED default trigger resolution and hw control

sequenceDiagram
    actor User as Userspace
    participant Sysfs as led_trigger_write
    participant LED as led_classdev
    participant TrigCore as led_trigger_set_default
    participant Match as led_match_default_trigger
    participant Mod as request_module_nowait
    participant TrigReg as led_trigger_register

    User->>Sysfs: Write("default") to trigger_file
    Sysfs->>LED: Get_led_cdev_from_kobj
    alt Buffer_is_default
        Sysfs->>TrigCore: led_trigger_set_default(led_cdev)
        alt Default_trigger_is_none
            TrigCore->>TrigCore: led_trigger_remove(led_cdev)
        else Named_default_trigger
            TrigCore->>TrigCore: Iterate_trigger_list
            TrigCore->>Match: led_match_default_trigger(led_cdev, trig)
            alt Trigger_found_and_relevant
                Match->>LED: led_trigger_set(led_cdev, trig)
            else Trigger_not_found
                TrigCore->>Mod: request_module_nowait(ledtrig:<name>)
            end
        end
    end

    TrigReg->>TrigCore: led_trigger_register(trig)
    TrigCore->>TrigCore: Iterate_leds_list
    TrigCore->>Match: led_match_default_trigger(led_cdev, trig)
    alt Match_success
        Match->>LED: led_trigger_set(led_cdev, trig)
    end

Loading

Class diagram for corepvt-ultrarisc DP1000 PVT hwmon driver

classDiagram
    class corepvt_channel_config {
        +const_char_pointer label
        +u32 trim
    }

    class corepvt_data {
        +const_hwmon_chip_info_pointer chip_info
        +u64 temp_chl_mask
        +u64 vol_chl_mask
    }

    class corepvt_hwmon {
        +struct_device_pointer dev
        +struct_device_pointer hwmon
        +void_pointer regs
        +int irq
        +int clk_freq
        +int channels
        +const_hwmon_chip_info_pointer chip_info
        +corepvt_channel_config config[PVT_MAX_CHANNEL]
        +const_corepvt_data_pointer pvt_data
        +raw_spinlock_t lock
        +int corepvt_read_vol(corepvt_hwmon_pointer pvt, int channel, long_pointer val)
        +int corepvt_read_temp(corepvt_hwmon_pointer pvt, int channel, long_pointer val)
        +umode_t corepvt_is_visible(const_void_pointer drvdata, enum_hwmon_sensor_types type, u32 attr, int channel)
        +int corepvt_read(struct_device_pointer dev, enum_hwmon_sensor_types type, u32 attr, int channel, long_pointer val)
        +int corepvt_read_string(struct_device_pointer dev, enum_hwmon_sensor_types type, u32 attr, int channel, const_char_pointer_pointer str)
        +int corepvt_init(corepvt_hwmon_pointer pvt)
        +int corepvt_probe_channel_from_dt(struct_platform_device_pointer pdev, corepvt_hwmon_pointer pvt)
        +int corepvt_probe(struct_platform_device_pointer pdev)
    }

    class hwmon_chip_info {
        +const_hwmon_ops_pointer ops
        +const_hwmon_channel_info_pointer_const_pointer info
    }

    class hwmon_ops {
        +umode_t_pointer is_visible
        +int_pointer read
        +int_pointer read_string
    }

    class hwmon_channel_info {
        +enum_hwmon_sensor_types type
        +u32_pointer config
    }

    corepvt_hwmon --> corepvt_channel_config : has_many
    corepvt_hwmon --> corepvt_data : uses
    corepvt_data --> hwmon_chip_info : provides
    hwmon_chip_info --> hwmon_ops : uses
    hwmon_chip_info --> hwmon_channel_info : describes

    class platform_driver_corepvt_driver {
        +int_pointer probe
        +struct_device_driver driver
    }

    platform_driver_corepvt_driver --> corepvt_hwmon : creates
    platform_driver_corepvt_driver --> corepvt_data : matches_via_of_match

Loading

File-Level Changes

Change	Details	Files
Implement UltraRISC CP100 PLIC claim-register erratum handling and related cleanups in the SiFive PLIC driver and bindings.	Rename the PLIC quirk bit to PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM and switch the compatible string from ultrarisc,dp1000-plic to ultrarisc,cp100-plic Change enable register handling to cache enable state in handler->enable_save on each toggle and stop saving it in suspend, relying on the cached values instead Introduce cp100_get_hwirq/cp100_isolate_pending_irq and plic_handle_irq_cp100 to temporarily mask all but the first pending interrupt before reading the claim register, then restore previous enables Select the chained handler function dynamically at probe time based on the quirk bit and use for_each_present_cpu in resume Simplify M-mode context init by zeroing entire enable register banks instead of per-IRQ toggling and adjust DT binding to require both dp1000-plic and cp100-plic compatibles	drivers/irqchip/irq-sifive-plic.c Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Extend the netdev LED trigger to support more link speeds, PHY offload, and dynamic visibility, and export it as a module alias.	Track supported link modes via an ethtool link settings snapshot and expose per-speed link_* attributes (10/100/1000/2500/5000/10000) with visibility gated by PHY capabilities Teach set_baseline_state and trigger work logic to handle the new high-speed link bits when deciding whether to blink Refresh supported link speed visibility on device_name changes and NETDEV_CHANGE events using a dedicated attribute group Integrate with hardware-controlled LEDs by caching hw_control, avoiding redundant baseline state programming, and using hw_control_get in netdev_trig_activate Register two attribute groups (generic trigger attributes and link-speed attributes) and add MODULE_ALIAS("ledtrig:netdev")	drivers/leds/trigger/ledtrig-netdev.c include/linux/leds.h Documentation/ABI/testing/sysfs-class-led-trigger-netdev
Add PHY-level LED hardware control for Realtek RTL8211F using netdev trigger rules.	Define RTL8211F LED control register layout, LED count, and bitfields for link/active modes Implement rtl8211f_led_hw_is_supported to validate requested trigger rules (subset of link speeds plus optional RX/TX, RX/TX must match, up to three LEDs) Implement rtl8211f_led_hw_control_get to read back current LED configuration and translate register bits into TRIGGER_NETDEV_* rules Implement rtl8211f_led_hw_control_set to program the LED control register (mode B) based on requested rules and hook these callbacks into the RTL8211F phy_driver	drivers/net/phy/realtek.c
Improve LED trigger/core behavior around default triggers, panic trigger takeover, and brightness setting error handling.	Make trigger_list local-static in led-triggers.c and stop exporting it in leds.h Allow writing "default" to the trigger sysfs file to re-apply the LED's default_trigger and show it in the trigger list formatting Refactor default-trigger selection into led_match_default_trigger, add support for "none" defaults (clearing triggers), and auto-request trigger modules if the named default is not yet registered During trigger registration, reuse led_match_default_trigger for newly created triggers to attach them to LEDs that want them Simplify ledtrig-panic by using the already-found global panic trigger pointer instead of scanning trigger_list, and ensure it disables delayed blinking immediately In led-core, treat ENOTSUPP from both async and blocking brightness callbacks as "no fixed brightness support" (no error), only log errors after filtering ENODEV for unplugged pluggable devices In led-class, if hw_control_trigger is set and no default_trigger is specified, automatically use the hw_control trigger as default before calling led_trigger_set_default	drivers/leds/led-triggers.c drivers/leds/trigger/ledtrig-panic.c drivers/leds/led-core.c drivers/leds/led-class.c drivers/leds/leds.h Documentation/ABI/testing/sysfs-class-led
Introduce an UltraRISC DP1000 core PVT hwmon driver with DT binding and hook it into the build.	Add CONFIG_SENSORS_COREPVT_ULTRARISC Kconfig entry and hook corepvt-ultrarisc.o into drivers/hwmon/Makefile Implement corepvt-ultrarisc platform hwmon driver that maps the PVT controller, configures PSCR/CFDR/CIR per channel based on clock-frequency, channels, and per-channel TRIM, and exposes temperature and voltage inputs via hwmon Use masks to map continuous temp/voltage channel blocks, implement label reporting per channel from DT child nodes, and protect register accesses with a raw spinlock Add DeviceTree binding ultrarisc,dp1000-pvt.yaml documenting top-level properties, per-channel child nodes, and an example DP1000 PVT node	drivers/hwmon/Kconfig drivers/hwmon/Makefile drivers/hwmon/corepvt-ultrarisc.c Documentation/devicetree/bindings/hwmon/ultrarisc,dp1000-pvt.yaml
Update UltraRISC DP1000 platform integration (PCIe, pinctrl, DTS, defconfig) for new naming, PLIC, PVT, and Titan board support.	Extend ultrarisc PCIe controller of_match table to match both ultrarisc,dp1000-pcie and ultrarisc,dw-pcie Fix the DP1000 pinctrl binding header file name and switch the board dtb name from dp1000-mo-v1 to dp1000-m0-v1 in the Ultrarisc DTS Makefile Adjust various Ultrarisc DP1000 DTS files (EVB, M0, Titan, common dtsi) to use the new pinctrl and PVT bindings and to expose Titan-specific features like PHY LED control (details in DTS diff) Update deepin_riscv64_desktop_defconfig to enable the new core PVT and LED/PHY features as needed	drivers/pci/controller/dwc/pcie-ultrarisc.c Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml arch/riscv/boot/dts/ultrarisc/Makefile arch/riscv/boot/dts/ultrarisc/dp1000-*.dtsi arch/riscv/configs/deepin_riscv64_desktop_defconfig

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[deepin-ci-robot]

Hi @WangJia-UR. Thanks for your PR.

I'm waiting for a deepin-community member to verify that this patch is reasonable to test. If it is, they should reply with /ok-to-test on its own line. Until that is done, I will not automatically test new commits in this PR, but the usual testing commands by org members will still work. Regular contributors should join the org to skip this step.

Once the patch is verified, the new status will be reflected by the ok-to-test label.

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[sourcery-ai]

Hey - I've found 3 issues, and left some high level feedback:

• In corepvt_probe_channel_from_dt(), you only consider children whose node name equals "channel", but the binding and example use channel@… nodes; this means no channels will be discovered in practice—consider matching via of_node_name_prefix(child, "channel") or using the unit address–style naming expected by the schema.
• The corepvt hwmon visibility logic currently only checks channel < pvt->channels and ignores temp_chl_mask/vol_chl_mask, so sysfs may expose channels for which no backing PVT channel or label exists; it would be more robust to derive visibility from the respective masks instead of just channels.
• In corepvt_probe(), error paths for devm_platform_ioremap_resource() and devm_hwmon_device_register_with_info() hardcode -EINVAL and manually call devm_kfree(), which both loses the original error and defeats devm—return PTR_ERR(...) directly and drop the explicit kfree.

Prompt for AI Agents

Please address the comments from this code review:

## Overall Comments
- In `corepvt_probe_channel_from_dt()`, you only consider children whose node name equals "channel", but the binding and example use `channel@…` nodes; this means no channels will be discovered in practice—consider matching via `of_node_name_prefix(child, "channel")` or using the unit address–style naming expected by the schema.
- The corepvt hwmon visibility logic currently only checks `channel < pvt->channels` and ignores `temp_chl_mask`/`vol_chl_mask`, so sysfs may expose channels for which no backing PVT channel or label exists; it would be more robust to derive visibility from the respective masks instead of just `channels`.
- In `corepvt_probe()`, error paths for `devm_platform_ioremap_resource()` and `devm_hwmon_device_register_with_info()` hardcode `-EINVAL` and manually call `devm_kfree()`, which both loses the original error and defeats devm—return `PTR_ERR(...)` directly and drop the explicit kfree.

## Individual Comments

### Comment 1
<location> `drivers/irqchip/irq-sifive-plic.c:636` </location>
<code_context>
-				void __iomem *enable_base = priv->regs +
-					CONTEXT_ENABLE_BASE +
-					i * CONTEXT_ENABLE_SIZE;
+				u32 __iomem *enable_base = priv->regs +	CONTEXT_ENABLE_BASE +
+							   i * CONTEXT_ENABLE_SIZE;

</code_context>

<issue_to_address>
**issue (bug_risk):** Off-by-one when clearing context enable words during probe

The loop `for (int j = 0; j <= nr_irqs / 32; j++)` iterates `nr_irqs / 32 + 1` times. When `nr_irqs` is a multiple of 32, this writes one word past the last valid enable register and may access undefined MMIO. Please bound by the actual number of 32-bit groups, e.g. `j < DIV_ROUND_UP(nr_irqs, 32)` or similar.
</issue_to_address>

### Comment 2
<location> `drivers/net/phy/realtek.c:546-555` </location>
<code_context>
+static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
+				       unsigned long rules)
+{
+	const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
+	u16 reg = 0;
+
+	if (index >= RTL8211F_LED_COUNT)
+		return -EINVAL;
+
+	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+		reg |= RTL8211F_LEDCR_LINK_10;
+
+	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+		reg |= RTL8211F_LEDCR_LINK_100;
+
+	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+		reg |= RTL8211F_LEDCR_LINK_1000;
+
+	if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
+	    test_bit(TRIGGER_NETDEV_TX, &rules)) {
+		reg |= RTL8211F_LEDCR_ACT_TXRX;
+	}
+
+	reg <<= RTL8211F_LEDCR_SHIFT * index;
+	reg |= RTL8211F_LEDCR_MODE;	 /* Mode B */
+
+	return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
</code_context>

<issue_to_address>
**issue (bug_risk):** RTL8211F LED mode bit handling appears misaligned for index > 0

`RTL8211F_LEDCR_MODE` (`BIT(15)`) looks like a global LED mode bit, but here it’s combined into `reg` and then shifted by `RTL8211F_LEDCR_SHIFT * index`. For `index > 0`, this moves the mode bit off bit 15, and the `mask` passed to `phy_modify_paged()` doesn’t cover it, so the mode will not be programmed as expected. You likely want to keep the mode bit unshifted and include it in the mask (if always forcing Mode B), or program it once independently of the per‑LED fields.
</issue_to_address>

### Comment 3
<location> `drivers/hwmon/corepvt-ultrarisc.c:282-284` </location>
<code_context>
+	if (!pvt)
+		return -ENOMEM;
+
+	pvt->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(pvt->regs)) {
+		dev_err(&pdev->dev, "get ioremap resource failed\n");
+		ret = -EINVAL;
+		goto free_pvt;
</code_context>

<issue_to_address>
**suggestion (bug_risk):** Error propagation from devm_platform_ioremap_resource and hwmon registration should preserve the original error code

You’re replacing the specific errno from `devm_platform_ioremap_resource()` / `devm_hwmon_device_register_with_info()` with `-EINVAL`, which obscures the real failure (e.g. `-ENOMEM`, `-EIO`) for callers and debugging. Instead, return `PTR_ERR(pvt->regs)` / `PTR_ERR(pvt->hwmon)` directly. Also, the `devm_kfree()` in the error path is unnecessary because `devm_kzalloc()` allocations are released automatically.

Suggested implementation:

```c
	pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL);
	if (!pvt)
		return -ENOMEM;

	pvt->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pvt->regs)) {
		ret = PTR_ERR(pvt->regs);
		dev_err(&pdev->dev, "get ioremap resource failed: %d\n", ret);
		return ret;
	}

	if (device_property_present(&pdev->dev, "interrupts"))
		pvt->irq = platform_get_irq(pdev, 0);

	ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq);
	if (ret) {
		dev_err(&pdev->dev, "get clock-frequency failed: %d\n", ret);
		return ret;
	}

```

1. Remove the `free_pvt:` label and any associated `devm_kfree(pvt);` (or similar manual cleanup of `pvt`) in `corepvt_probe()`, as `pvt` is allocated with `devm_kzalloc()` and will be freed automatically.
2. If there is a similar error path for `devm_hwmon_device_register_with_info()` that currently overwrites its error code with a fixed errno (e.g. `-EINVAL`) or uses `goto free_pvt`, update it to:
   * capture the return value in `ret`,
   * log it (optionally including the errno), and
   * `return ret;` directly instead of using the `free_pvt` path.
</issue_to_address>

---

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[deepin-ci-robot]

[APPROVALNOTIFIER] This PR is APPROVED

This pull-request has been approved by: opsiff

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[Copilot]

Pull request overview

This pull request adds support for UltraRISC DP1000 platform features including core PVT monitoring, PHY LED control on MilkV Titan, and PLIC interrupt controller errata handling. It backports several upstream features and updates device tree configurations.

• Adds UltraRISC DP1000 core PVT hwmon driver for temperature and voltage monitoring
• Enables hardware-controlled PHY LEDs on Realtek RTL8211F with netdev trigger support
• Implements CP100 PLIC claim register erratum workaround
• Extends netdev LED triggers to support higher link speeds (2.5G, 5G, 10G)

Reviewed changes

Copilot reviewed 27 out of 28 changed files in this pull request and generated 14 comments.

Show a summary per file

File	Description
drivers/hwmon/corepvt-ultrarisc.c	New hwmon driver for DP1000 PVT sensor monitoring
drivers/net/phy/realtek.c	Adds LED hardware control support for RTL8211F PHY
drivers/irqchip/irq-sifive-plic.c	Implements CP100 claim register erratum workaround
drivers/leds/trigger/ledtrig-netdev.c	Adds 2.5G/5G/10G link speed support and visibility control
drivers/leds/led-*.c	Enhances LED trigger core with default trigger support
drivers/pci/controller/dwc/pcie-ultrarisc.c	Adds DP1000-specific PCIe compatible string
arch/riscv/boot/dts/ultrarisc/*	Updates device trees with cache info, PVT nodes, and board configs
include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h	Adds pinctrl definitions for DP1000
Documentation/*	Updates binding docs for PLIC, hwmon, and LED ABI

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

[Copilot]

Use C-style comments (/* */) instead of C++-style comments (//) for consistency with Linux kernel coding style.

Suggested change

	// Assume that the voltage channel is continuous
	/* Assume that the voltage channel is continuous */

[Copilot]

Use C-style comments (/* */) instead of C++-style comments (//) for consistency with Linux kernel coding style.

Suggested change

	// Config and enable corepvt
	/* Config and enable corepvt */

[Copilot]

The compatible string ordering in the PLIC binding documentation is incorrect. According to the binding pattern, the compatible should list the most specific first, then the fallback. The code shows "ultrarisc,cp100-plic", "ultrarisc,dp1000-plic" but the binding documentation shows them in reverse order. This mismatch needs to be corrected.

Suggested change

	- const: ultrarisc,dp1000-plic
	- const: ultrarisc,cp100-plic
	- const: ultrarisc,cp100-plic
	- const: ultrarisc,dp1000-plic

[Copilot]

All error paths using 'goto free_pvt' should be changed to 'return ret' directly since the devm_kfree is unnecessary. This affects lines 286, 295, 301, 308, and 327.

[Copilot]

Use C-style comments (/* */) instead of C++-style comments (//) for consistency with Linux kernel coding style.

[Copilot]

The goto label 'free_pvt' is unnecessary because devm_kzalloc automatically frees the memory when the device is unbound. The explicit devm_kfree call on line 339 is redundant and should be removed along with the goto.

Suggested change

devm_kfree(&pdev->dev, pvt);

[Copilot]

The interrupts property documentation states it is optional, but the 'required' section at line 57 does not list it, which is correct. However, the description on line 26 should more clearly indicate it's optional by starting with "Optional:" or similar wording for clarity.

Suggested change

	description: Optional interrupt number for the PVT controller. This property is optional and can be omitted if not used.
	description: Optional: interrupt number for the PVT controller. This property can be omitted if not used.

[Copilot]

Using Chinese full-width comma (，) in multiple cache description comments. These should be changed to use standard ASCII punctuation for consistency. This issue appears in multiple L2 and L3 cache descriptions throughout the file.

[Copilot]

The XOR logic check is incorrect. The condition checks if "RX is not set XOR TX is not set", which means it returns an error when both are set or both are unset. This is the opposite of the intended behavior described in the comment. The condition should be: if ((rules & BIT(TRIGGER_NETDEV_RX)) ^ (rules & BIT(TRIGGER_NETDEV_TX))) to ensure both are either set together or unset together.

Suggested change

	if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
	if ((rules & BIT(TRIGGER_NETDEV_RX)) ^ (rules & BIT(TRIGGER_NETDEV_TX)))

[Copilot]

Using Chinese full-width comma (，) in comments instead of ASCII comma (,). This should be changed to use standard ASCII punctuation for consistency with the rest of the codebase.

Suggested change

	* 8-way set associative，size 512KB
	* 8-way set associative, size 512KB