Support corepvt, phy leds on titan and update dts

Documentation/ABI/testing/sysfs-class-led

@@ -72,6 +72,12 @@ Description:
 		/sys/class/leds/<led> once a given trigger is selected. For
 		their documentation see `sysfs-class-led-trigger-*`.
 
+		Writing "none" removes the trigger for this LED.
+
+		Writing "default" sets the trigger to the LED's default trigger
+		(which would often be configured in the device tree for the
+		hardware).
+
 What:		/sys/class/leds/<led>/inverted
 Date:		January 2011
 KernelVersion:	2.6.38

Documentation/ABI/testing/sysfs-class-led-trigger-netdev

@@ -88,6 +88,8 @@ Description:
 		speed of 10MBps of the named network device.
 		Setting this value also immediately changes the LED state.
 
+		Present only if the named network device supports 10Mbps link speed.
+
 What:		/sys/class/leds/<led>/link_100
 Date:		Jun 2023
 KernelVersion:	6.5
@@ -101,6 +103,8 @@ Description:
 		speed of 100Mbps of the named network device.
 		Setting this value also immediately changes the LED state.
 
+		Present only if the named network device supports 100Mbps link speed.
+
 What:		/sys/class/leds/<led>/link_1000
 Date:		Jun 2023
 KernelVersion:	6.5
@@ -114,6 +118,53 @@ Description:
 		speed of 1000Mbps of the named network device.
 		Setting this value also immediately changes the LED state.
 
+		Present only if the named network device supports 1000Mbps link speed.
+
+What:		/sys/class/leds/<led>/link_2500
+Date:		Nov 2023
+KernelVersion:	6.8
+Contact:	[email protected]
+Description:
+		Signal the link speed state of 2500Mbps of the named network device.
+
+		If set to 0 (default), the LED's normal state is off.
+
+		If set to 1, the LED's normal state reflects the link state
+		speed of 2500Mbps of the named network device.
+		Setting this value also immediately changes the LED state.
+
+		Present only if the named network device supports 2500Mbps link speed.
+
+What:		/sys/class/leds/<led>/link_5000
+Date:		Nov 2023
+KernelVersion:	6.8
+Contact:	[email protected]
+Description:
+		Signal the link speed state of 5000Mbps of the named network device.
+
+		If set to 0 (default), the LED's normal state is off.
+
+		If set to 1, the LED's normal state reflects the link state
+		speed of 5000Mbps of the named network device.
+		Setting this value also immediately changes the LED state.
+
+		Present only if the named network device supports 5000Mbps link speed.
+
+What:		/sys/class/leds/<led>/link_10000
+Date:		Nov 2023
+KernelVersion:	6.8
+Contact:	[email protected]
+Description:
+		Signal the link speed state of 10000Mbps of the named network device.
+
+		If set to 0 (default), the LED's normal state is off.
+
+		If set to 1, the LED's normal state reflects the link state
+		speed of 10000Mbps of the named network device.
+		Setting this value also immediately changes the LED state.
+
+		Present only if the named network device supports 10000Mbps link speed.
+
 What:		/sys/class/leds/<led>/half_duplex
 Date:		Jun 2023
 KernelVersion:	6.5

Documentation/devicetree/bindings/hwmon/ultrarisc,dp1000-pvt.yaml

@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/ultrarisc,dp1000-pvt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 Core PVT Sensor
+
+maintainers:
+  - Jia Wang <[email protected]>
+
+description: |
+  UltraRISC DP1000 SoC provides a voltage and temperature (PVT) sensor to
+  monitor the internal SoC environment including chip temperature and supply voltage.
+
+properties:
+  compatible:
+    const: ultrarisc,dp1000-pvt
+
+  reg:
+    maxItems: 1
+    description: Register space of the PVT controller
+
+  interrupts:
+    maxItems: 1
+    description: Optional interrupt number for the PVT controller. This property is optional and can be omitted if not used.
+
+  clock-frequency:
+    description: Clock frequency of the PVT controller in Hz
+
+  channels:
+    description: Total number of PVT channels supported
+
+patternProperties:
+  "^channel@[0-9a-f]+$":
+    type: object
+    description: Child node describing a PVT channel
+    properties:
+      reg:
+        description: Channel index
+        minimum: 0
+        maximum: 63
+
+      label:
+        description: Name for this channel, typically indicating its purpose
+
+      trim:
+        description: Trim value for calibration
+        default: 7
+        minimum: 0
+        maximum: 15
+
+    required:
+      - reg
+      - label
+
+required:
+  - compatible
+  - reg
+  - clock-frequency
+  - channels
+
+additionalProperties: false
+
+examples:
+  - |
+    core_pvt: pvt@20008000 {
+        compatible = "ultrarisc,dp1000-pvt";
+        reg = <0x20008000 0x1000>;
+        clock-frequency = <4000000>;
+        channels = <13>;
+
+        channel@0 {
+            reg = <0>;
+            label = "Core temp0";
+            trim = <7>;
+        };
+
+        channel@1 {
+            reg = <1>;
+            label = "Core temp1";
+            trim = <7>;
+        };
+
+        channel@2 {
+            reg = <2>;
+            label = "Core temp2";
+            trim = <7>;
+        };
+    };

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

@@ -67,6 +67,9 @@ properties:
               - allwinner,sun20i-d1-plic
               - thead,th1520-plic
           - const: thead,c900-plic
+      - items:
+          - const: ultrarisc,dp1000-plic
+          - const: ultrarisc,cp100-plic
       - items:
           - const: sifive,plic-1.0.0
           - const: riscv,plic0

Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml

@@ -10,7 +10,7 @@ maintainers:
 
 description: |
   UltraRISC RISC-V SoC DP1000 pin controller.
-  <dt-bindings/pinctrl/ur-dp1000-pinctrl.h> contains the pinmux definitions.
+  <dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h> contains the pinmux definitions.
 
 properties:
   compatible:

arch/riscv/boot/dts/ultrarisc/Makefile

@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb
-dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb
+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-m0-v1.dtb
 dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb

arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi

@@ -3,7 +3,7 @@
  * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
  */
 
-#include <dt-bindings/pinctrl/ur-dp1000-pinctrl.h>
+#include <dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h>
 #include "dp1000.dtsi"
 
 &pmx0 {

arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts

@@ -5,11 +5,14 @@
 
 #include "dp1000-evb-pinctrl.dtsi"
 #include <dt-bindings/iio/temperature/thermocouple.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
+	model = "UltraRISC EVB v1";
+	compatible = "ultrarisc,evb-v1", "ultrarisc,dp1000";
+
 	chosen {
-		bootargs = "earlycon=sbi console=ttyS1,115200";
-		stdout-path = &uart1;
+		stdout-path = "serial1:115200n8";
 	};
 };
 
@@ -21,6 +24,16 @@
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
+
+	rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
 };
 
 &i2c3 {
@@ -31,14 +44,6 @@
 &spi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi0_pins>;
-
-	mmc0: mmc@0 {
-		compatible = "mmc-spi-slot";
-		spi-max-frequency = <15625000>;
-		reg = <0x00>;
-		voltage-ranges = <3300 3300>;
-		disable-wp;
-	};
 };
 
 &spi1 {
@@ -62,3 +67,17 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
 };
+
+&ethernet {
+	phy-handle = <&phy0>;
+	mdio {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		compatible = "snps,dwmac-mdio";
+		phy0: phy@0{
+			phandle = <0x04>;
+			reg = <0x00>;
+			status = "okay";
+		};
+	};
+};

arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi → arch/riscv/boot/dts/ultrarisc/dp1000-m0-pinctrl.dtsi

@@ -3,7 +3,7 @@
  * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
  */
 
-#include <dt-bindings/pinctrl/ur-dp1000-pinctrl.h>
+#include <dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h>
 #include "dp1000.dtsi"
 
 &pmx0 {

arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts → arch/riscv/boot/dts/ultrarisc/dp1000-m0-v1.dts

@@ -3,13 +3,32 @@
  * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
  */
 
-#include "dp1000-mo-pinctrl.dtsi"
+#include "dp1000-m0-pinctrl.dtsi"
 #include <dt-bindings/iio/temperature/thermocouple.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
+	model = "Rongda M0 Board v1";
+	compatible = "rongda,m0-v1", "ultrarisc,dp1000";
+
 	chosen {
-		bootargs = "earlycon=sbi console=ttyS0,115200";
-		stdout-path = &uart0;
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <&portb 0 GPIO_ACTIVE_HIGH>;
+		active-delay-ms = <100>;
+		line-name = "power-off";
+		status = "okay";
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&portb 1 GPIO_ACTIVE_HIGH>;
+		active-delay-ms = <100>;
+		line-name = "reset-system";
+		status = "okay";
 	};
 };
 
@@ -64,3 +83,17 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
 };
+
+&ethernet {
+	phy-handle = <&phy0>;
+	mdio {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		compatible = "snps,dwmac-mdio";
+		phy0: phy@0{
+			phandle = <0x04>;
+			reg = <0x00>;
+			status = "okay";
+		};
+	};
+};

arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi

@@ -3,7 +3,7 @@
  * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd.
  */
 
-#include <dt-bindings/pinctrl/ur-dp1000-pinctrl.h>
+#include <dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h>
 #include "dp1000.dtsi"
 
 &pmx0 {
@@ -129,23 +129,19 @@
 		UR_DP1000_IOMUX_A  1  UR_FUNC0
 		UR_DP1000_IOMUX_A  2  UR_FUNC0
 		UR_DP1000_IOMUX_A  3  UR_FUNC0
-		UR_DP1000_IOMUX_A  4  UR_FUNC0
 		>;
 
 		pinconf-pins = <
 		UR_DP1000_IOMUX_A  0   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
 		UR_DP1000_IOMUX_A  1   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
 		UR_DP1000_IOMUX_A  2   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
 		UR_DP1000_IOMUX_A  3   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
-		UR_DP1000_IOMUX_A  4   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
 		>;
 	};
 
 	gpios_pin: gpios_pin {
 		pinctrl-pins = <
 		UR_DP1000_IOMUX_A  10  UR_FUNC_DEF
-		UR_DP1000_IOMUX_A  11  UR_FUNC_DEF
-		UR_DP1000_IOMUX_A  14  UR_FUNC_DEF
 		UR_DP1000_IOMUX_A  15  UR_FUNC_DEF
 
 		UR_DP1000_IOMUX_B  0   UR_FUNC_DEF
@@ -158,8 +154,6 @@
 
 		pinconf-pins = <
 		UR_DP1000_IOMUX_A  10   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
-		UR_DP1000_IOMUX_A  11   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
-		UR_DP1000_IOMUX_A  14   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
 		UR_DP1000_IOMUX_A  15   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)
 
 		UR_DP1000_IOMUX_B  0   UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF)