SystemVerilog: ignore default_nettype directive

regression/verilog/directives/default_nettype1.desc

@@ -0,0 +1,7 @@
+CORE
+default_nettype1.sv
+
+^no properties$
+^EXIT=10$
+^SIGNAL=0$
+--

regression/verilog/directives/default_nettype1.sv

@@ -0,0 +1,5 @@
+`default_nettype none
+`default_nettype wire
+
+module main;
+endmodule

src/verilog/scanner.l

@@ -556,6 +556,7 @@ prove           { VL2SMV_VERILOG_KEYWORD(TOK_PROVE); }
 \'line          { continue; }
 \'file          { continue; }
 \`line{WS}[^\n]*{NL} { line_directive(); continue; }
+\`default_nettype{WS}[^\n]*{NL} { /* ignore for now */ continue; }
 \`{Word}        { preprocessor(); continue; }
 
 \f              { /* ignore */ }

src/verilog/verilog_preprocessor.cpp

@@ -608,6 +608,21 @@ void verilog_preprocessort::directive()
     // ignored
     tokenizer().skip_until_eol();
   }
+  else if(text == "default_nettype")
+  {
+    // pass through
+    out << '`' << text;
+    while(true)
+    {
+      auto token = tokenizer().peek();
+      if(token.is_eof())
+        break;
+      out << token.text;
+      tokenizer().next_token(); // eat
+      if(token == '\n')
+        break;
+    }
+  }
   else
   {
     // check defines