example: Hazard3 CPU #626
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example: Hazard3 CPU #626
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tautschnig
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Oct 21, 2024
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| # expected elaboration-time constant, but got `hazard3_muldiv_seq.properties.i' | ||
| # $past, for loop | ||
| # ebmc -I hdl -D HAZARD3_ASSERTIONS --systemverilog --bound 0 hdl/arith/hazard3_muldiv_seq.v |
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Do those issues still persist?
examples/Hazard3/Hazard3.sh
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| # clone Hazard3 repo if not done yet | ||
| if [ ! -e Hazard3/.git ] ; then | ||
| git clone https://github.com/Wren6991/Hazard3 | ||
| (cd Hazard3 ; git checkout v1.0) |
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How about git clone —branch v1.0 —depth 1
examples/Hazard3/Hazard3.sh
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| -D HAZARD3_ASSERTIONS --bound 0 \ | ||
| hdl/arith/hazard3_shift_barrel.v | ||
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| # conflicting assignment types |
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Here and below: do those persist? If so, can we have KNOWNBUG tests for them?
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Yes; one test added, the other one linked as a comment
The Hazard3 RISC-V CPU comes with SVA assertions. This script downloads the RTL, and runs ebmc to check them.
Romy15200
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example: Hazard3 CPU
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The Hazard3 RISC-V CPU comes with SVA assertions. This script downloads the RTL, and runs ebmc to check them.