Verilog: set defines on command line #627
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tautschnig
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Shouldn't there also be a test that actually seeks to parse the result after preprocessing (with command-line set defines)? |
This allows setting SystemVerilog preprocessor defines on the command line with -D.
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Verilog: set defines on command line
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This allows setting SystemVerilog preprocessor defines on the command line with
-D.