Phase 4

Added Floating point coprocessor(Floating Point ALU and change in Datapath)
Added 8 new tests

Phase 3

changed our architecture from single cycle to pipelined MIPS
code refactored and cleaned

Phase 2

L1 Cache added
Added 4 clock memory latency to Main Memmory
4 new Tests added
LB and SB commands added

Phase 1

Single Cycle Mips Processor
16 test (assembly programms)
support for all R type and I type and j,jr,jal commnads