[WIP] Update directories and linker tests

llvm · Sep 5, 2024 · eeb8041 · eeb8041
1 parent 36d2c64
commit eeb8041
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Showing 5 changed files with 18 additions and 41 deletions.
diff --git a/include/circt/Dialect/OM/OMOps.td b/include/circt/Dialect/OM/OMOps.td
@@ -116,6 +116,7 @@ def ClassFieldsOp : OMClassFieldsLike<"class.fields", [HasParent<"ClassOp">]> {
     }]>
   ];
   let arguments = (ins Variadic<AnyType>:$fields);
+  // TODO: remove attrs
   //                      ArrayAttr:$fieldNames,
   //                      DictionaryAttr:$fieldIdxs);
 

diff --git a/test/Dialect/FIRRTL/SFCTests/directories.fir b/test/Dialect/FIRRTL/SFCTests/directories.fir
@@ -135,41 +135,23 @@ circuit TestHarness:
 ; SITEST_NODUT:     FILE "testbench.sitest.json"
 ; SITEST_NODUT-NOT: FILE
 
-; MLIR_OUT:  om.class @SitestBlackBoxModulesSchema(%basepath: !om.basepath, %moduleName_in: !om.string) {
-; MLIR_OUT:    om.class.fields(
-; MLIR_OUT:      moduleName %moduleName_in : !om.string
-; MLIR_OUT:    )
+; MLIR_OUT:  om.class @SitestBlackBoxModulesSchema(%basepath: !om.basepath, %moduleName_in: !om.string) -> (moduleName: !om.string) {
+; MLIR_OUT:    om.class.fields %moduleName_in : !om.string
 ; MLIR_OUT:  }
 
-; MLIR_OUT:  om.class @SitestBlackBoxMetadata(%basepath: !om.basepath)
+; MLIR_OUT:  om.class @SitestBlackBoxMetadata(%basepath: !om.basepath) -> [[V1:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>, [[V2:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>, [[V3:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>
 ; MLIR_OUT:    %0 = om.constant "Foo_BlackBox" : !om.string
 ; MLIR_OUT:    %1 = om.object @SitestBlackBoxModulesSchema(%basepath, %0) : (!om.basepath, !om.string) -> !om.class.type<@SitestBlackBoxModulesSchema>
 ; MLIR_OUT:    %2 = om.constant "Bar_BlackBox" : !om.string
 ; MLIR_OUT:    %3 = om.object @SitestBlackBoxModulesSchema(%basepath, %2) : (!om.basepath, !om.string) -> !om.class.type<@SitestBlackBoxModulesSchema>
 ; MLIR_OUT:    %4 = om.constant "Baz_BlackBox" : !om.string
 ; MLIR_OUT:    %5 = om.object @SitestBlackBoxModulesSchema(%basepath, %4) : (!om.basepath, !om.string) -> !om.class.type<@SitestBlackBoxModulesSchema>
-; MLIR_OUT:    om.class.fields(
-; MLIR_OUT:      [[V1:.+]] %1 : !om.class.type<@SitestBlackBoxModulesSchema>,
-; MLIR_OUT:      [[V2:.+]] %3 : !om.class.type<@SitestBlackBoxModulesSchema>,
-; MLIR_OUT:      [[V3:.+]] %5 : !om.class.type<@SitestBlackBoxModulesSchema>
-; MLIR_OUT:    )
+; MLIR_OUT:    om.class.fields %1, %3, %5 : !om.class.type<@SitestBlackBoxModulesSchema>, !om.class.type<@SitestBlackBoxModulesSchema>, !om.class.type<@SitestBlackBoxModulesSchema>
 ; MLIR_OUT:  }
 
-; MLIR_OUT:  om.class @MemorySchema(%basepath: !om.basepath, %name_in: !om.string, %depth_in: !om.integer, %width_in: !om.integer, %maskBits_in: !om.integer, %readPorts_in: !om.integer, %writePorts_in: !om.integer, %readwritePorts_in: !om.integer, %writeLatency_in: !om.integer, %readLatency_in: !om.integer, %hierarchy_in: !om.list<!om.path>, %inDut_in: i1, %extraPorts_in: !om.list<!om.class.type<@ExtraPortsMemorySchema>>
-; MLIR_OUT:    om.class.fields(
-; MLIR_OUT:      name %name_in : !om.string,
-; MLIR_OUT:      depth %depth_in : !om.integer,
-; MLIR_OUT:      width %width_in : !om.integer,
-; MLIR_OUT:      maskBits %maskBits_in : !om.integer,
-; MLIR_OUT:      readPorts %readPorts_in : !om.integer,
-; MLIR_OUT:      writePorts %writePorts_in : !om.integer,
-; MLIR_OUT:      readwritePorts %readwritePorts_in : !om.integer,
-; MLIR_OUT:      writeLatency %writeLatency_in : !om.integer,
-; MLIR_OUT:      readLatency %readLatency_in : !om.integer,
-; MLIR_OUT:      hierarchy %hierarchy_in : !om.list<!om.path>,
-; MLIR_OUT:      extraPorts %extraPorts_in : !om.list<!om.class.type<@ExtraPortsMemorySchema>>
-; MLIR_OUT:    )
-; MLIR_OUT:  om.class @MemoryMetadata(%basepath: !om.basepath)
+; MLIR_OUT:  om.class @MemorySchema(%basepath: !om.basepath, %name_in: !om.string, %depth_in: !om.integer, %width_in: !om.integer, %maskBits_in: !om.integer, %readPorts_in: !om.integer, %writePorts_in: !om.integer, %readwritePorts_in: !om.integer, %writeLatency_in: !om.integer, %readLatency_in: !om.integer, %hierarchy_in: !om.list<!om.path>, %inDut_in: i1, %extraPorts_in: !om.list<!om.class.type<@ExtraPortsMemorySchema>> -> (name: !om.string, depth: !om.integer, width: !om.integer, maskBits: !om.integer, readPorts: !om.integer, writePorts: !om.integer, readWritePorts: !om.integer, writeLatency: !om.integer, readLatency: !om.integer, hierarchy: !om.list<!om.path>, extraPorts: !om.list<!om.class.type<@ExtraPortsMemorySchema>>)
+; MLIR_OUT:    om.class.fields %name_in, %depth_in, %width_in, %maskBits_in, %readPorts_in, %writePorts_in, %readwritePorts_in, %writeLatency_in, %readLatency_in, %hierarchy_in, %extraPorts_in : !om.string, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.integer, !om.list<!om.path>, !om.list<!om.class.type<@ExtraPortsMemorySchema>>
+; MLIR_OUT:  om.class @MemoryMetadata(%basepath: !om.basepath) -> (foo_m_ext_field:, bar_m_ext_field:, baz_m_ext_field:)
 ; MLIR_OUT:     om.path_create instance %basepath @memNLA
 ; MLIR_OUT:     om.list_create
 ; MLIR_OUT:     om.object @MemorySchema
@@ -207,11 +189,7 @@ circuit TestHarness:
 ; MLIR_OUT:     om.constant #om.integer<0 : ui32> : !om.integer
 ; MLIR_OUT:     om.constant #om.integer<1 : ui32> : !om.integer
 ; MLIR_OUT:     om.constant #om.integer<1 : ui32> : !om.integer
-; MLIR_OUT:     om.class.fields(
-; MLIR_OUT:       foo_m_ext_field
-; MLIR_OUT:       bar_m_ext_field
-; MLIR_OUT:       baz_m_ext_field
-; MLIR_OUT:     )
+; MLIR_OUT:     om.class.fields %4, %20, %38 : !om.class.type<@MemorySchema>, !om.class.type<@MemorySchema>, ! om.class.type<@MemorySchema>
 
 ; SITEST_NODUT:     FILE "design.sitest.json"
 ; SITEST_NODUT-NOT: FILE

diff --git a/test/om-linker/Inputs/a.mlir b/test/om-linker/Inputs/a.mlir
@@ -1,8 +1,8 @@
 module {
   om.class @A(%arg: i1) {
-    om.class.fields()
+    om.class.fields
   }
   om.class @Conflict(){
-    om.class.fields()
+    om.class.fields
   }
 }
diff --git a/test/om-linker/Inputs/b.mlir b/test/om-linker/Inputs/b.mlir
@@ -1,11 +1,9 @@
 module {
-  om.class.extern @A(%arg: i1) {
-    om.class.extern.fields()
-  }
+  om.class.extern @A(%arg: i1) {}
   om.class @B(%arg: i2) {
-    om.class.fields()
+    om.class.fields
   }
   om.class @Conflict(){
-    om.class.fields()
+    om.class.fields
   }
 }
diff --git a/test/om-linker/link.mlir b/test/om-linker/link.mlir
@@ -1,15 +1,15 @@
 // RUN: om-linker %S/Inputs/a.mlir %S/Inputs/b.mlir %S/Inputs/other.mlir | FileCheck %s
 // CHECK:      module {
 // CHECK-NEXT:   om.class @A(%arg: i1) {
-// CHECK-NEXT:     om.class.fields()
+// CHECK-NEXT:     om.class.fields
 // CHECK-NEXT:   }
 // CHECK-NEXT:   om.class @Conflict_a() {
-// CHECK-NEXT:     om.class.fields()
+// CHECK-NEXT:     om.class.fields
 // CHECK-NEXT:   }
 // CHECK-NEXT:   om.class @B(%arg: i2) {
-// CHECK-NEXT:     om.class.fields()
+// CHECK-NEXT:     om.class.fields
 // CHECK-NEXT:   }
 // CHECK-NEXT:   om.class @Conflict_b() {
-// CHECK-NEXT:     om.class.fields()
+// CHECK-NEXT:     om.class.fields
 // CHECK-NEXT:   }
 // CHECK-NEXT: }