[Moore] Introduce Mem2Reg to eliminate local variables

include/circt/Dialect/Moore/MooreOps.h

@@ -18,6 +18,7 @@
 #include "circt/Dialect/Moore/MooreTypes.h"
 #include "mlir/Interfaces/ControlFlowInterfaces.h"
 #include "mlir/Interfaces/InferTypeOpInterface.h"
+#include "mlir/Interfaces/MemorySlotInterfaces.h"
 
 #define GET_OP_CLASSES
 #include "circt/Dialect/Moore/MooreEnums.h.inc"

include/circt/Dialect/Moore/MooreOps.td

@@ -180,6 +180,7 @@ def ProcedureOp : MooreOp<"procedure", [
 //===----------------------------------------------------------------------===//
 
 def VariableOp : MooreOp<"variable", [
+  DeclareOpInterfaceMethods<PromotableAllocationOpInterface>,
   DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
   OptionalTypesMatchWith<"initial value and variable types match",
     "result", "initial", "cast<RefType>($_self).getNestedType()">
@@ -251,6 +252,7 @@ def NetOp : MooreOp<"net", [
 }
 
 def ReadOp : MooreOp<"read", [
+  DeclareOpInterfaceMethods<PromotableMemOpInterface>,
   TypesMatchWith<"input and result types match",
     "result", "input", "RefType::get(cast<UnpackedType>($_self))">
 ]> {
@@ -291,7 +293,9 @@ def ContinuousAssignOp : AssignOpBase<"assign", [HasParent<"SVModuleOp">]> {
   }];
 }
 
-def BlockingAssignOp : AssignOpBase<"blocking_assign"> {
+def BlockingAssignOp : AssignOpBase<"blocking_assign", [
+  DeclareOpInterfaceMethods<PromotableMemOpInterface>
+]> {
   let summary = "Blocking procedural assignment";
   let description = [{
     A blocking procedural assignment in a sequential block, such as `x = y`. The

lib/Dialect/Moore/CMakeLists.txt

@@ -19,6 +19,7 @@ add_circt_dialect_library(CIRCTMoore
   CIRCTSupport
   MLIRIR
   MLIRInferTypeOpInterface
+  MLIRMemorySlotInterfaces
 )
 
 add_dependencies(circt-headers MLIRMooreIncGen)

lib/Dialect/Moore/MooreOps.cpp

@@ -19,6 +19,7 @@
 
 using namespace circt;
 using namespace circt::moore;
+using namespace mlir;
 
 //===----------------------------------------------------------------------===//
 // SVModuleOp
@@ -237,6 +238,33 @@ void VariableOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
   setNameFn(getResult(), getName());
 }
 
+llvm::SmallVector<MemorySlot> VariableOp::getPromotableSlots() {
+  if (isa<SVModuleOp>(getOperation()->getParentOp()))
+    return {};
+  return {MemorySlot{getResult(), getType()}};
+}
+
+Value VariableOp::getDefaultValue(const MemorySlot &slot, OpBuilder &builder) {
+  if (auto value = getInitial())
+    return value;
+  return builder.create<ConstantOp>(
+      getLoc(),
+      cast<moore::IntType>(cast<RefType>(slot.elemType).getNestedType()), 0);
+}
+
+void VariableOp::handleBlockArgument(const MemorySlot &slot,
+                                     BlockArgument argument,
+                                     OpBuilder &builder) {}
+
+::std::optional<::mlir::PromotableAllocationOpInterface>
+VariableOp::handlePromotionComplete(const MemorySlot &slot, Value defaultValue,
+                                    OpBuilder &builder) {
+  if (defaultValue.use_empty())
+    defaultValue.getDefiningOp()->erase();
+  this->erase();
+  return std::nullopt;
+}
+
 //===----------------------------------------------------------------------===//
 // NetOp
 //===----------------------------------------------------------------------===//
@@ -419,6 +447,78 @@ OpFoldResult BoolCastOp::fold(FoldAdaptor adaptor) {
   return {};
 }
 
+//===----------------------------------------------------------------------===//
+// BlockingAssignOp
+//===----------------------------------------------------------------------===//
+
+bool BlockingAssignOp::loadsFrom(const MemorySlot &slot) { return false; }
+
+bool BlockingAssignOp::storesTo(const MemorySlot &slot) {
+  return getDst() == slot.ptr;
+}
+
+Value BlockingAssignOp::getStored(const MemorySlot &slot, OpBuilder &builder,
+                                  Value reachingDef,
+                                  const DataLayout &dataLayout) {
+  return getSrc();
+}
+
+bool BlockingAssignOp::canUsesBeRemoved(
+    const MemorySlot &slot, const SmallPtrSetImpl<OpOperand *> &blockingUses,
+    SmallVectorImpl<OpOperand *> &newBlockingUses,
+    const DataLayout &dataLayout) {
+
+  if (blockingUses.size() != 1)
+    return false;
+  Value blockingUse = (*blockingUses.begin())->get();
+  return blockingUse == slot.ptr && getDst() == slot.ptr &&
+         getSrc() != slot.ptr &&
+         getSrc().getType() == cast<RefType>(slot.elemType).getNestedType();
+}
+
+DeletionKind BlockingAssignOp::removeBlockingUses(
+    const MemorySlot &slot, const SmallPtrSetImpl<OpOperand *> &blockingUses,
+    OpBuilder &builder, Value reachingDefinition,
+    const DataLayout &dataLayout) {
+  return DeletionKind::Delete;
+}
+
+//===----------------------------------------------------------------------===//
+// ReadOp
+//===----------------------------------------------------------------------===//
+
+bool ReadOp::loadsFrom(const MemorySlot &slot) {
+  return getOperand() == slot.ptr;
+}
+
+bool ReadOp::storesTo(const MemorySlot &slot) { return false; }
+
+Value ReadOp::getStored(const MemorySlot &slot, OpBuilder &builder,
+                        Value reachingDef, const DataLayout &dataLayout) {
+  llvm_unreachable("getStored should not be called on ReadOp");
+}
+
+bool ReadOp::canUsesBeRemoved(const MemorySlot &slot,
+                              const SmallPtrSetImpl<OpOperand *> &blockingUses,
+                              SmallVectorImpl<OpOperand *> &newBlockingUses,
+                              const DataLayout &dataLayout) {
+
+  if (blockingUses.size() != 1)
+    return false;
+  Value blockingUse = (*blockingUses.begin())->get();
+  return blockingUse == slot.ptr && getOperand() == slot.ptr &&
+         getResult().getType() == cast<RefType>(slot.elemType).getNestedType();
+}
+
+DeletionKind
+ReadOp::removeBlockingUses(const MemorySlot &slot,
+                           const SmallPtrSetImpl<OpOperand *> &blockingUses,
+                           OpBuilder &builder, Value reachingDefinition,
+                           const DataLayout &dataLayout) {
+  getResult().replaceAllUsesWith(reachingDefinition);
+  return DeletionKind::Delete;
+}
+
 //===----------------------------------------------------------------------===//
 // TableGen generated logic.
 //===----------------------------------------------------------------------===//

test/Dialect/Moore/mem2reg.mlir

@@ -0,0 +1,35 @@
+// RUN: circt-opt --mem2reg %s | FileCheck %s
+
+// CHECK-LABEL: moore.module @LocalVar() {
+moore.module @LocalVar() {
+// CHECK: %x = moore.variable : <i32>
+// CHECK: %y = moore.variable : <i32>
+// CHECK: %z = moore.variable : <i32>
+%x = moore.variable : <i32>
+%y = moore.variable : <i32>
+%z = moore.variable : <i32>
+moore.procedure always_comb {
+    // CHECK: %0 = moore.read %x : i32
+    // CHECK: %1 = moore.constant 1 : i32
+    // CHECK: %2 = moore.add %0, %1 : i32
+    // CHECK: moore.blocking_assign %z, %2 : i32
+    // CHECK: %3 = moore.constant 1 : i32
+    // CHECK: %4 = moore.add %2, %3 : i32
+    // CHECK: moore.blocking_assign %y, %4 : i32
+    %a = moore.variable : <i32>
+    %0 = moore.read %x : i32
+    %1 = moore.constant 1 : i32
+    %2 = moore.add %0, %1 : i32
+    moore.blocking_assign %a, %2 : i32
+    %3 = moore.read %a : i32
+    moore.blocking_assign %z, %3 : i32
+    %4 = moore.read %a : i32
+    %5 = moore.constant 1 : i32
+    %6 = moore.add %4, %5 : i32
+    moore.blocking_assign %a, %6 : i32
+    %7 = moore.read %a : i32
+    moore.blocking_assign %y, %7 : i32
+}
+// CHECK: moore.output
+moore.output
+}

tools/circt-opt/circt-opt.cpp

@@ -72,6 +72,7 @@ int main(int argc, char **argv) {
 
   // Register test passes
   circt::test::registerAnalysisTestPasses();
+  mlir::registerMem2RegPass();
 
   return mlir::failed(mlir::MlirOptMain(
       argc, argv, "CIRCT modular optimizer driver", registry));

tools/circt-verilog/CMakeLists.txt

@@ -6,6 +6,7 @@ llvm_update_compile_flags(circt-verilog)
 
 target_link_libraries(circt-verilog PRIVATE
   CIRCTImportVerilog
+  CIRCTMooreToCore
   CIRCTSupport
   MLIRIR
 )

tools/circt-verilog/circt-verilog.cpp

@@ -13,10 +13,12 @@
 //===----------------------------------------------------------------------===//
 
 #include "circt/Conversion/ImportVerilog.h"
+#include "circt/Conversion/MooreToCore.h"
 #include "circt/Support/Version.h"
 #include "mlir/IR/BuiltinOps.h"
 #include "mlir/Pass/PassManager.h"
 #include "mlir/Support/FileUtilities.h"
+#include "mlir/Transforms/Passes.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/InitLLVM.h"
 #include "llvm/Support/SourceMgr.h"
@@ -31,7 +33,14 @@ using namespace circt;
 //===----------------------------------------------------------------------===//
 
 namespace {
-enum class LoweringMode { OnlyPreprocess, OnlyLint, OnlyParse, Full };
+enum class LoweringMode {
+  OnlyPreprocess,
+  OnlyLint,
+  OnlyParse,
+  OutputIRMoore,
+  OutputIRHW,
+  Full
+};
 
 struct CLOptions {
   cl::OptionCategory cat{"Verilog Frontend Options"};
@@ -60,7 +69,13 @@ struct CLOptions {
                      "CIRCT IR"),
           clEnumValN(LoweringMode::OnlyParse, "parse-only",
                      "Only parse and elaborate the input, without mapping to "
-                     "CIRCT IR")),
+                     "CIRCT IR"),
+          clEnumValN(LoweringMode::OutputIRMoore, "ir-moore",
+                     "Run the entire pass manager to just before MooreToCore "
+                     "conversion, and emit the resulting Moore dialect IR"),
+          clEnumValN(LoweringMode::OutputIRHW, "ir-hw",
+                     "Run the MooreToCore conversion and emit the resulting "
+                     "core dialect IR")),
       cl::init(LoweringMode::Full), cl::cat(cat)};
 
   //===--------------------------------------------------------------------===//
@@ -200,6 +215,23 @@ struct CLOptions {
 
 static CLOptions opts;
 
+/// Parse specified files that had been translated into Moore dialect IR. After
+/// that simplify these files like deleting local variables, and then emit the
+/// resulting Moore dialect IR .
+static LogicalResult populateMooreTransforms(mlir::PassManager &pm) {
+  pm.addPass(mlir::createMem2Reg());
+  // TODO: like dedup pass.
+
+  return success();
+}
+
+/// Convert Moore dialect IR into core dialect IR
+static LogicalResult populateMooreToCoreLowering(mlir::PassManager &pm) {
+  pm.addPass(createConvertMooreToCorePass());
+
+  return success();
+}
+
 //===----------------------------------------------------------------------===//
 // Implementation
 //===----------------------------------------------------------------------===//
@@ -269,6 +301,23 @@ static LogicalResult executeWithSources(MLIRContext *context,
   if (failed(importVerilog(sourceMgr, context, ts, module.get(), &options)))
     return failure();
 
+  PassManager pm(context);
+  if (opts.loweringMode == LoweringMode::OutputIRMoore ||
+      opts.loweringMode == LoweringMode::OutputIRHW) {
+
+    // Simplify the Moore dialect IR.
+    if (failed(populateMooreTransforms(pm)))
+      return failure();
+
+    if (opts.loweringMode == LoweringMode::OutputIRHW)
+      // Convert Moore IR into core IR.
+      if (failed(populateMooreToCoreLowering(pm)))
+        return failure();
+  }
+
+  if (failed(pm.run(module.get())))
+    return failure();
+
   // Print the final MLIR.
   module->print(outputFile->os());
   outputFile->keep();