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[HW][SV] Transition "HWToSV" to "ProceduralCoreToSV" pass. #7335
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,26 @@ | ||
//===- ProceduralCoreToSV.h - Porcedural Core to SV pass entry point ------===// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This header file defines prototypes that expose the declarations for the | ||
// procedural core to SV lowering pass. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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#ifndef CIRCT_CONVERSION_PROCEDURALCORETOSV_H | ||
#define CIRCT_CONVERSION_PROCEDURALCORETOSV_H | ||
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#include "circt/Support/LLVM.h" | ||
#include <memory> | ||
namespace circt { | ||
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#define GEN_PASS_DECL_PROCEDURALCORETOSV | ||
#include "circt/Conversion/Passes.h.inc" | ||
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} // namespace circt | ||
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#endif // CIRCT_CONVERSION_PROCEDURALCORETOSV_H |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,75 @@ | ||
//===- ProceduralCoreToSV.cpp - Procedural Core To SV Conversion Pass -----===// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// Lower procedural core dialect (HW/Sim) operations to the SV dialect. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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#include "circt/Conversion/ProceduralCoreToSV.h" | ||
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#include "circt/Dialect/SV/SVDialect.h" | ||
#include "circt/Dialect/SV/SVOps.h" | ||
#include "circt/Dialect/Sim/SimDialect.h" | ||
#include "circt/Dialect/Sim/SimOps.h" | ||
#include "mlir/Dialect/SCF/IR/SCF.h" | ||
#include "mlir/IR/Threading.h" | ||
#include "mlir/Pass/Pass.h" | ||
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namespace circt { | ||
#define GEN_PASS_DEF_PROCEDURALCORETOSV | ||
#include "circt/Conversion/Passes.h.inc" | ||
} // namespace circt | ||
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using namespace circt; | ||
using namespace mlir; | ||
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static sv::EventControl hwToSvEventControl(hw::EventControl ec) { | ||
switch (ec) { | ||
case hw::EventControl::AtPosEdge: | ||
return sv::EventControl::AtPosEdge; | ||
case hw::EventControl::AtNegEdge: | ||
return sv::EventControl::AtNegEdge; | ||
case hw::EventControl::AtEdge: | ||
return sv::EventControl::AtEdge; | ||
} | ||
llvm_unreachable("Unknown event control kind"); | ||
} | ||
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namespace { | ||
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struct ProceduralOpRewriter : public RewriterBase { | ||
ProceduralOpRewriter(MLIRContext *ctxt) : RewriterBase::RewriterBase(ctxt) {} | ||
}; | ||
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struct ProceduralCoreToSVPass | ||
: public circt::impl::ProceduralCoreToSVBase<ProceduralCoreToSVPass> { | ||
ProceduralCoreToSVPass() = default; | ||
void runOnOperation() override; | ||
}; | ||
} // namespace | ||
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void ProceduralCoreToSVPass::runOnOperation() { | ||
hw::HWModuleOp theModule = getOperation(); | ||
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ProceduralOpRewriter rewriter(theModule.getContext()); | ||
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theModule.walk<mlir::WalkOrder::PreOrder>([&](hw::TriggeredOp triggeredOp) | ||
-> WalkResult { | ||
// Create an AlwaysOp, move the body over and remove the TriggeredOp | ||
rewriter.setInsertionPoint(triggeredOp); | ||
auto alwaysOp = rewriter.create<sv::AlwaysOp>( | ||
triggeredOp.getLoc(), | ||
ArrayRef<sv::EventControl>{hwToSvEventControl(triggeredOp.getEvent())}, | ||
ArrayRef<Value>{triggeredOp.getTrigger()}); | ||
rewriter.mergeBlocks(triggeredOp.getBodyBlock(), alwaysOp.getBodyBlock(), | ||
triggeredOp.getInputs()); | ||
rewriter.eraseOp(triggeredOp); | ||
// Don't recurse into the body. | ||
return WalkResult::skip(); | ||
}); | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -3349,6 +3349,22 @@ void TriggeredOp::build(OpBuilder &builder, OperationState &odsState, | |
b->addArguments(inputs.getTypes(), argLocs); | ||
} | ||
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LogicalResult TriggeredOp::verify() { | ||
if (!!getOperation()->getParentOfType<hw::TriggeredOp>()) | ||
return emitOpError("must not be nested under another TriggeredOp."); | ||
Comment on lines
+3353
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+3354
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Can we add `hasParentOp<"hw::HWModuleOp"> to TriggeredOp instead? |
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return success(); | ||
} | ||
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LogicalResult TriggeredOp::verifyRegions() { | ||
auto numInputs = getInputs().size(); | ||
auto numArgs = getBodyBlock()->getNumArguments(); | ||
if (numInputs != numArgs) | ||
return emitOpError("number of inputs (" + Twine(numInputs) + | ||
") does not match number of body arguments (" + | ||
Twine(numArgs) + ")."); | ||
return success(); | ||
} | ||
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//===----------------------------------------------------------------------===// | ||
// TableGen generated logic. | ||
//===----------------------------------------------------------------------===// | ||
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2 changes: 1 addition & 1 deletion
2
test/Conversion/HWToSV/test_trigger.mlir → ...sion/ProceduralCoreToSV/test_trigger.mlir
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Was a there specific reason that removes OpConversion pattern and does manual walk? I think we generally prefer OpConversion pattern for the maintainability.