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[Arc] Fully support initialization through seq.initial #7605
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This is really really cool! Thanks for adding support for this to Arc 🥳 🙏
OpBuilder builder(reg); | ||
auto init = builder | ||
.create<mlir::UnrealizedConversionCastOp>( | ||
reg.getLoc(), reg.getType(), reg.getInitialValue()) | ||
.getResult(0); |
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I'm wondering if it might be worthwhile having an immutable<T> -> T
cast operation, something like seq.unwrap_immutable
. That could also enable some canonicalizations where a seq.compreg
could lower to its initial value if it provably can never change.
Unrealized conversion cast also works though 😃
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Or we might reconsider supporting arc.initial
before lower state and do the conversion to it in ConvertToArcs?
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seq.unwrap_immutable
sounds reasonable and will follow-up. arc.initial
might work but currently arc.initial
doesn't produce any value and we need to allocate states for them. So I guess there would be a big overlap with LowerState. Another approach might be to change arc.state
's initial value operand to take seq.immutable
type instead of a normal integer.
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Really cool work! Just a bit puzzled about the integration test results 🤔
for (Operation &op : *module.getBodyBlock()) { | ||
if (isa<seq::InitialOp>(&op)) { | ||
initialOps.push_back(cast<seq::InitialOp>(&op)); | ||
continue; | ||
} |
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Nit: can remove braces for consistency
@@ -236,8 +242,9 @@ hw.module @Trivial(in %clock: !seq.clock, in %i0: i4, in %reset: i1, out out: i4 | |||
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// CHECK-LABEL: hw.module @TrivialWithInit( | |||
hw.module @TrivialWithInit(in %clock: !seq.clock, in %i0: i4, in %reset: i1, out out: i4) { | |||
// CHECK: [[CST2:%.+]] = hw.constant 2 : i4 | |||
// CHECK: [[RES0:%.+]] = arc.state @[[TRIVIALINIT_ARC]](%i0) clock %clock reset %reset initial ([[CST2]] : i4) latency 1 {names = ["foo"] | |||
// CHECK: %[[INIT:.+]] = seq.initial { |
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Nit:
// CHECK: %[[INIT:.+]] = seq.initial { | |
// CHECK: %[[INIT:.+]] = seq.initial { |
// RUN: arcilator %s --run --jit-entry=main | FileCheck %s | ||
// REQUIRES: arcilator-jit | ||
|
||
// CHECK: o1 = 10 |
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Shouldn't this be 16, or am I missing something?
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circt/lib/Conversion/ArcToLLVM/LowerArcToLLVM.cpp
Lines 539 to 540 in bba8cfb
formatStr.append("%zx\n"); | |
SmallVector<char> formatStrVec{formatStr.begin(), formatStr.end()}; |
It is printed in hex but yeah, it's a bit confusing so I'll change to use a smaller number.
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Oh, totally forgot about that. Maybe we should prepend a 0x
to this format string. Or a smaller number, a comment, or using 0x10
at the constant op would be nice 🙂
OpBuilder builder(reg); | ||
auto init = builder | ||
.create<mlir::UnrealizedConversionCastOp>( | ||
reg.getLoc(), reg.getType(), reg.getInitialValue()) | ||
.getResult(0); |
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Or we might reconsider supporting arc.initial
before lower state and do the conversion to it in ConvertToArcs?
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Thank you for the review! I'm going to merge this and will follow up how to deal with unrealized conversion cast. |
This PR implements state initialization using
seq.initial
not limited to constants. Combined with #7606 we can perform random initialization in arcilator