[FIRRTL] Lower firrtl.simulation to verif.simulation #8312
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Add the `firrtl.simulation` op, which declares a simulation unit test and references a module to act as the top-level for the simulation. The target module must have exactly four ports, clock, init, done, and success, with corresponding directions and types. This new op is analogous to the `firrtl.formal` op. Also add support for a `simulation` construct in the parser, also analogous to the `formal` construct. A later commit will add a lowering to `verif.formal`.
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Add a lowering from `firrtl.simulation` to `verif.simulation` in the FIRRTL-to-HW conversion. The lowering creates a `verif.simulation` op that simply instantiates the module pointed to by `firrtl.simulation`, connecting its `clock` and `init` ports to the simulation op's block arguments, and yielding the `done` and `success` ports back. We may want to inline the instance in the future, but that is purely cosmetic. This now allows FIR files to contain `simulation` unit tests that can be lowered to HW through `firtool` and then executed using `arcilator`.
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Add a lowering from
firrtl.simulationtoverif.simulationin the FIRRTL-to-HW conversion. The lowering creates averif.simulationop that simply instantiates the module pointed to byfirrtl.simulation, connecting itsclockandinitports to the simulation op's block arguments, and yielding thedoneandsuccessports back. We may want to inline the instance in the future, but that is purely cosmetic.This now allows FIR files to contain
simulationunit tests that can be lowered to HW throughfirtooland then executed usingarcilator.