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[PyRTG] Switch to new immediates #8316

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Apr 1, 2025
Merged

[PyRTG] Switch to new immediates #8316

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2 changes: 1 addition & 1 deletion frontends/PyRTG/src/pyrtg/__init__.py
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Expand Up @@ -14,4 +14,4 @@
from .bags import Bag
from .sequences import sequence, Sequence, RandomizedSequence
from .target import target, entry
from .resources import IntegerRegister, Imm5, Imm12, Imm13, Imm21, Imm32
from .resources import IntegerRegister, Immediate
78 changes: 7 additions & 71 deletions frontends/PyRTG/src/pyrtg/resources.py
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Expand Up @@ -12,86 +12,22 @@
from typing import Union


class Imm5(Value):
class Immediate(Value):

def __init__(self, value: Union[ir.Value, int]) -> Imm5:
def __init__(self, width: int, value: Union[ir.Value, int]) -> Immediate:
self._width = width
self._value = value

def _get_ssa_value(self) -> ir.Value:
if isinstance(self._value, int):
self = rtgtest.ImmediateOp(rtgtest.Imm5Attr.get(self._value))
self = rtg.ConstantOp(rtg.ImmediateAttr.get(self._width, self._value))
return self._value

def get_type(self) -> ir.Type:
return type()
return rtg.ImmediateType.get(self._width)

def type(*args: ir.Type) -> ir.Type:
return rtgtest.Imm5Type.get()


class Imm12(Value):

def __init__(self, value: Union[ir.Value, int]) -> Imm12:
self._value = value

def _get_ssa_value(self) -> ir.Value:
if isinstance(self._value, int):
self = rtgtest.ImmediateOp(rtgtest.Imm12Attr.get(self._value))
return self._value

def type(*args: ir.Type) -> ir.Type:
return rtgtest.Imm12Type.get()


class Imm13(Value):

def __init__(self, value: Union[ir.Value, int]) -> Imm13:
self._value = value

def _get_ssa_value(self) -> ir.Value:
if isinstance(self._value, int):
self = rtgtest.ImmediateOp(rtgtest.Imm13Attr.get(self._value))
return self._value

def get_type(self) -> ir.Type:
return type()

def type(*args: ir.Type) -> ir.Type:
return rtgtest.Imm12Type.get()


class Imm21(Value):

def __init__(self, value: Union[ir.Value, int]) -> Imm21:
self._value = value

def _get_ssa_value(self) -> ir.Value:
if isinstance(self._value, int):
self = rtgtest.ImmediateOp(rtgtest.Imm21Attr.get(self._value))
return self._value

def get_type(self) -> ir.Type:
return type()

def type(*args: ir.Type) -> ir.Type:
return rtgtest.Imm21Type.get()


class Imm32(Value):

def __init__(self, value: Union[ir.Value, int]) -> Imm32:
self._value = value

def _get_ssa_value(self) -> ir.Value:
if isinstance(self._value, int):
self = rtgtest.ImmediateOp(rtgtest.Imm32Attr.get(self._value))
return self._value

def get_type(self) -> ir.Type:
return type()

def type(*args: ir.Type) -> ir.Type:
return rtgtest.Imm32Type.get()
def type(width: int) -> ir.Type:
return rtg.ImmediateType.get(width)


class IntegerRegister(Value):
Expand Down
18 changes: 3 additions & 15 deletions frontends/PyRTG/src/pyrtg/support.py
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Expand Up @@ -31,21 +31,9 @@ def _FromCirctValue(value: ir.Value) -> Value:
if isinstance(type, rtgtest.IntegerRegisterType):
from .resources import IntegerRegister
return IntegerRegister(value)
if isinstance(type, rtgtest.Imm5Type):
from .resources import Imm5
return Imm5(value)
if isinstance(type, rtgtest.Imm12Type):
from .resources import Imm12
return Imm12(value)
if isinstance(type, rtgtest.Imm13Type):
from .resources import Imm13
return Imm13(value)
if isinstance(type, rtgtest.Imm21Type):
from .resources import Imm21
return Imm21(value)
if isinstance(type, rtgtest.Imm32Type):
from .resources import Imm32
return Imm32(value)
if isinstance(type, rtg.ImmediateType):
from .resources import Immediate
return Immediate(type.width, value)
assert False, "Unsupported value"


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28 changes: 14 additions & 14 deletions frontends/PyRTG/test/basic.py
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Expand Up @@ -2,7 +2,7 @@
# RUN: %rtgtool% %s --seed=0 --output-format=elaborated | FileCheck %s --check-prefix=ELABORATED
# RUN: %rtgtool% %s --seed=0 -o %t --output-format=asm && FileCheck %s --input-file=%t --check-prefix=ASM

from pyrtg import test, sequence, target, entry, rtg, Label, Set, Integer, Bag, rtgtest, Imm5, Imm12, Imm13, Imm21, Imm32, IntegerRegister
from pyrtg import test, sequence, target, entry, rtg, Label, Set, Integer, Bag, rtgtest, Immediate, IntegerRegister

# MLIR-LABEL: rtg.target @Tgt0 : !rtg.dict<entry0: !rtg.set<index>>
# MLIR-NEXT: [[C0:%.+]] = index.constant 0
Expand Down Expand Up @@ -261,29 +261,29 @@ def test_labels():


# MLIR-NEXT: rtg.test @test_registers_and_immediates()
# MLIR-NEXT: [[IMM32:%.+]] = rtgtest.immediate #rtgtest.imm32<32> : !rtgtest.imm32
# MLIR-NEXT: [[IMM21:%.+]] = rtgtest.immediate #rtgtest.imm21<16> : !rtgtest.imm21
# MLIR-NEXT: [[IMM13:%.+]] = rtgtest.immediate #rtgtest.imm13<9> : !rtgtest.imm13
# MLIR-NEXT: [[IMM32:%.+]] = rtg.constant #rtg.isa.immediate<32, 32>
# MLIR-NEXT: [[IMM21:%.+]] = rtg.constant #rtg.isa.immediate<21, 16>
# MLIR-NEXT: [[IMM13:%.+]] = rtg.constant #rtg.isa.immediate<13, 9>
# MLIR-NEXT: [[T2:%.+]] = rtg.fixed_reg #rtgtest.t2 : !rtgtest.ireg
# MLIR-NEXT: [[IMM5:%.+]] = rtgtest.immediate #rtgtest.imm5<4> : !rtgtest.imm5
# MLIR-NEXT: [[IMM5:%.+]] = rtg.constant #rtg.isa.immediate<5, 4>
# MLIR-NEXT: [[T1:%.+]] = rtg.fixed_reg #rtgtest.t1 : !rtgtest.ireg
# MLIR-NEXT: [[IMM12:%.+]] = rtgtest.immediate #rtgtest.imm12<8> : !rtgtest.imm12
# MLIR-NEXT: [[IMM12:%.+]] = rtg.constant #rtg.isa.immediate<12, 8>
# MLIR-NEXT: [[T0:%.+]] = rtg.fixed_reg #rtgtest.t0 : !rtgtest.ireg
# MLIR-NEXT: [[VREG:%.+]] = rtg.virtual_reg [#rtgtest.t0 : !rtgtest.ireg, #rtgtest.t1 : !rtgtest.ireg, #rtgtest.t2 : !rtgtest.ireg, #rtgtest.t3 : !rtgtest.ireg, #rtgtest.t4 : !rtgtest.ireg, #rtgtest.t5 : !rtgtest.ireg, #rtgtest.t6 : !rtgtest.ireg, #rtgtest.a7 : !rtgtest.ireg, #rtgtest.a6 : !rtgtest.ireg, #rtgtest.a5 : !rtgtest.ireg, #rtgtest.a4 : !rtgtest.ireg, #rtgtest.a3 : !rtgtest.ireg, #rtgtest.a2 : !rtgtest.ireg, #rtgtest.a1 : !rtgtest.ireg, #rtgtest.a0 : !rtgtest.ireg, #rtgtest.s1 : !rtgtest.ireg, #rtgtest.s2 : !rtgtest.ireg, #rtgtest.s3 : !rtgtest.ireg, #rtgtest.s4 : !rtgtest.ireg, #rtgtest.s5 : !rtgtest.ireg, #rtgtest.s6 : !rtgtest.ireg, #rtgtest.s7 : !rtgtest.ireg, #rtgtest.s8 : !rtgtest.ireg, #rtgtest.s9 : !rtgtest.ireg, #rtgtest.s10 : !rtgtest.ireg, #rtgtest.s11 : !rtgtest.ireg, #rtgtest.s0 : !rtgtest.ireg, #rtgtest.ra : !rtgtest.ireg, #rtgtest.sp : !rtgtest.ireg]
# MLIR-NEXT: rtgtest.rv32i.addi [[VREG]], [[T0]], [[IMM12]]
# MLIR-NEXT: rtgtest.rv32i.slli [[VREG]], [[T1]], [[IMM5]]
# MLIR-NEXT: rtgtest.rv32i.beq [[VREG]], [[T2]], [[IMM13]] : !rtgtest.imm13
# MLIR-NEXT: rtgtest.rv32i.jal [[VREG]], [[IMM21]] : !rtgtest.imm21
# MLIR-NEXT: rtgtest.rv32i.auipc [[VREG]], [[IMM32]] : !rtgtest.imm32
# MLIR-NEXT: rtgtest.rv32i.beq [[VREG]], [[T2]], [[IMM13]] : !rtg.isa.immediate<13>
# MLIR-NEXT: rtgtest.rv32i.jal [[VREG]], [[IMM21]] : !rtg.isa.immediate<21>
# MLIR-NEXT: rtgtest.rv32i.auipc [[VREG]], [[IMM32]] : !rtg.isa.immediate<32>
# MLIR-NEXT: }


@test()
def test_registers_and_immediates():
vreg = IntegerRegister.virtual()
imm12 = Imm12(8)
imm12 = Immediate(12, 8)
rtgtest.ADDI(vreg, IntegerRegister.t0(), imm12)
rtgtest.SLLI(vreg, IntegerRegister.t1(), Imm5(4))
rtgtest.BEQ(vreg, IntegerRegister.t2(), Imm13(9))
rtgtest.JAL(vreg, Imm21(16))
rtgtest.AUIPC(vreg, Imm32(32))
rtgtest.SLLI(vreg, IntegerRegister.t1(), Immediate(5, 4))
rtgtest.BEQ(vreg, IntegerRegister.t2(), Immediate(13, 9))
rtgtest.JAL(vreg, Immediate(21, 16))
rtgtest.AUIPC(vreg, Immediate(32, 32))
20 changes: 2 additions & 18 deletions lib/Bindings/Python/support.py
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Expand Up @@ -154,27 +154,11 @@ def type_to_pytype(t) -> ir.Type:
except ValueError:
pass
try:
return rtgtest.IntegerRegisterType(t)
except ValueError:
pass
try:
return rtgtest.Imm5Type(t)
except ValueError:
pass
try:
return rtgtest.Imm12Type(t)
return rtg.ImmediateType(t)
except ValueError:
pass
try:
return rtgtest.Imm13Type(t)
except ValueError:
pass
try:
return rtgtest.Imm21Type(t)
except ValueError:
pass
try:
return rtgtest.Imm32Type(t)
return rtgtest.IntegerRegisterType(t)
except ValueError:
pass

Expand Down