firtool-1.67.1

Full Changelog: firtool-1.67.0...firtool-1.67.1

firtool-1.68.0

What's Changed

• [ImportVerilog] Add assignment statements by @fabianschuiki in #6773
• [WireDFT] Remove WireDFT by @nandor in #6761
• [SV] Use a symbol in macro identifiers by @nandor in #6777
• [Sim] Emit a SYNTHESIS macro declaration if needed by @nandor in #6778
• [SV] Verify macro reference symbols by @nandor in #6780
• [FIRRTL] Handle reference ports when Classes dedup. by @mikeurbach in #6770
• LLVM bump by @prithayan in #6782
• [Seq] Allow presets for more types on firreg by @nandor in #6781
• [OM] Add C API and Python bindings for EvaluatorValue::Reference. by @mikeurbach in #6785
• Bump LLVM to 1e828f838cc0f15074f3dbbb04929c06ef0c9729. by @mikeurbach in #6784
• [FIRTOOL] Move LowerIntrinsic to preprocess by @uenoku in #6796

Full Changelog: firtool-1.67.0...firtool-1.68.0

firtool-1.67.0

What's Changed

• [LLVM] Bump by @nandor in #6718
• [FIRRTL] Update HierPathOps in LowerLayers by @seldridge in #6721
• [ESI][Runtime] Use std::future in channel reads and func calls by @teqdruid in #6723
• [FIRRTL] Add integer addition conversion to LowerClasses. by @mikeurbach in #6710
• [OM] Support integer binary arithmetic in the Evaluator. by @mikeurbach in #6711
• [FIRTOOL] More sane chisel interface directory handling by @darthscsi in #6687
• [FIRRTL] Prevent divison by zero in CreateSiFiveMetadata by @fzi-hielscher in #6726
• [ImportVerilog] Add translation, run Slang compilation by @fabianschuiki in #6708
• [FIRRTL] Support PropertyType in emitConnect. by @mikeurbach in #6734
• [PyCDE] Wrappers for Ibis classes by @teqdruid in #6631
• [FIRRTL] Check unknown width and reset rules during parsing 4.0.0. by @dtzSiFive in #6731
• [Sim] Introduce wrappers on top of sv.finish/sv.fatal by @nandor in #6737
• [FIRRTL][CAPI] Add function for importing annotations by @SpriteOvO in #6730
• [Emit] Organize output files using the emit dialect by @nandor in #6727
• [ExportVerilog][Emit] Export emitted files by @nandor in #6728
• [Emit] Emit black boxes through emit ops by @nandor in #6729
• [ImportVerilog] Convert empty modules and instances by @fabianschuiki in #6743
• [FIRRTL][LowerLayers] Clean up names of artifacts generated by layers by @rwy7 in #6733
• [Ibis] Split ContainerOp in two by @teqdruid in #6739
• [Emit] Emit SV ops nested in a file by @nandor in #6744
• [FIRRTL][FIRParser] Enforce 4.0.0 main module must be public. by @dtzSiFive in #6747
• [Emit] Use FileOp to emit metadata by @nandor in #6746
• [MSFT][Emit] Replace output_file with an emit::File by @nandor in #6751
• [Emit] Convert the ExtractInstances pass to use file ops by @nandor in #6756
• [ExtractInstances] Fix Windows CI by @nandor in #6758
• [HGLDD] Fix instance output port emission by @fabianschuiki in #6750
• [HGLDD] Uniquify object names during emission by @fabianschuiki in #6753
• [HW to BTOR2] Add support for initial values by @dobios in #6754
• [ImportVerilog] Add type conversion and basic variables by @fabianschuiki in #6755
• [ESI][Runtime] Building wheels by @teqdruid in #6759
• [HW] Remove the file list attribute from HW by @nandor in #6757
• [ESI][Runtime] Build and publish wheels by @teqdruid in #6763
• [FIRRTL] Put layer collateral in testbench dir by @seldridge in #6741
• [ESI] Move entirely over to the runtime for testing by @teqdruid in #6764
• [Emit] Introduce emit.ref to pull ops into file bodies by @nandor in #6762
• [Calyx] Switch sequential memories to be true single port memories by @andrewb1999 in #6765
• [ImportVerilog] Convert initial/always/final procedures by @fabianschuiki in #6766
• [Calyx] Fix memory import locations by @andrewb1999 in #6769
• [arcilator] Introduce simulation orchestration subdialect by @Moxinilian in #6695
• [FIRRTL] Use the class map in ObjectOp parser. by @mikeurbach in #6771
• [capi][python] Add Emit Dialect by @seldridge in #6774

Full Changelog: firtool-1.66.0...firtool-1.67.0

firtool-1.66.0

What's Changed

• [HW] Lower hw.instance_choice to SV by @nandor in #6624
• [ESI][Runtime] Convert Type& to Type* by @teqdruid in #6644
• [ESI][Runtime][NFC] Move requestChannelsFor into accelerator connection by @teqdruid in #6646
• [ESI][Runtime] Add the notion of a Context by @teqdruid in #6647
• [ESI][Runtime][NFC] Switch from ptr,size to MessageData by @teqdruid in #6648
• Fix some issues in the LayerBlockOp verifier by @rwy7 in #6654
• [FIRRTL] Use set-based logic to test for layer compatibility by @rwy7 in #6643
• [FIRRTL] Intrinsics: Fix mistakenly preserved analyses. by @dtzSiFive in #6666
• [OM] Remove Symbol trait from ClassFieldLikes. by @mikeurbach in #6665
• [Calyx] Make ControlOp a SymbolTable. by @mikeurbach in #6670
• [IMCP] Fix a race condition regarding aggregate preservation by @uenoku in #6671
• Track instance layers by @rwy7 in #6663
• [CI] Add statically linked CIRCT full build to ReleaseArtifact CI by @uenoku in #6544
• [FIRRTL] chisel_{assert_assume,assume,cover,ifelsefatal} intrinsics. by @dtzSiFive in #6664
• [ImportVerilog] Add import options and Verilog preprocessing by @fabianschuiki in #6632
• Allow propassign under layerblocks by @rwy7 in #6656
• [Seq] Remove Symbol trait from HLMemOp. by @mikeurbach in #6676
• [ESI][Runtime] Adding support for FuncService by @teqdruid in #6673
• [FIRRTL] InferResets: verify that FART annotation is on async resets by @youngar in #6674
• [FSM] Remove Symbol trait from InstanceOp and HWInstanceOp. by @mikeurbach in #6675
• [FIRRTL][LowerXMR] Use FIRRTL 4.0 ref ABI. by @dtzSiFive in #6677
• Tree-wide test fixes for FileCheck directive typos by @dtzSiFive in #6679
• [LowerIntrinsics] Accept EICG_wrapper without test_en, reject annos by @fabianschuiki in #6678
• [WireDFT] Disable the pass by default by @nandor in #6684
• [LowerToHW] Fix shr(0-bit, n) lowering by @seldridge in #6683
• [ImportVerilog] Fix single unit preprocessor option by @fabianschuiki in #6682
• [arcilator] Remove PrintStateInfo pass by @Moxinilian in #6529
• LLVM bump by @darthscsi in #6662
• Make circt-verilog available to integration tests. by @dtzSiFive in #6685
• [LowerClasses] Lower classes that instantiate properties. by @mikeurbach in #6688
• [FIRRTL] Add layer-associated Probes to LowerLayers pass by @seldridge in #6554
• [ExportVerilog] Fix crash on sv.reg with initial value by @fzi-hielscher in #6689
• [HW] Encode the option group name in instance choice ops by @nandor in #6645
• [HW] HWModule: store input port locations only on block args by @youngar in #6642
• [FIRRTL] Add parser version APIs that accept an SMLoc, NFC. by @mikeurbach in #6692
• [FIRRTL] Provide a way to override inferReturnTypes in FIRRTLExprOp. by @mikeurbach in #6697
• [FIRRTL] Add integer addition property op. by @mikeurbach in #6691
• [OM] Add rationale for expressions. by @mikeurbach in #6702
• [OM] Add OpInterface for IntegerBinaryArithmeticOp. by @mikeurbach in #6703
• [PyCDE] Refactor Input/Output ports to extend property by @teqdruid in #6700
• [FIRRTL] Add integer addition parser support. by @mikeurbach in #6701
• [CMake] Make ImportVerilog compile-time depend on slang by @fzi-hielscher in #6707
• [FIRRTL][Lower-Layers] do not capture uses multiple times by @rwy7 in #6699
• [FIRRTL] Change min width of shr for UInt to 0 by @jackkoenig in #6698
• [FIRRTL] Use untyped propassign source accessor in LowerClasses. by @mikeurbach in #6690
• [OM] Add integer addition op. by @mikeurbach in #6704

New Contributors

• @Moxinilian made their first contribution in #6529

Full Changelog: firtool-1.65.0...firtool-1.66.0

firtool-1.65.0

What's Changed

• [FIRRTL] Add parser/emitter support for layer-associated probes by @seldridge in #6552
• [scf-to-calyx]delete identifiers. by @linuxlonelyeagle in #6611
• [HW] Remove the cache-based lookup method from HWInstanceLike by @nandor in #6622
• [FIRRTL] Use isX intrinsic for trueOrIsX verif statements. by @dtzSiFive in #6625
• [ImportVerilog] Add Slang frontend dependency by @fabianschuiki in #6620
• [HW][CAPI] Add instance graph C-API for iterating modules by @SpriteOvO in #6626
• [FIRParser] Allow assert stmt to have a format string by @uenoku in #6621
• [ESI][Runtime] Support Questa by @teqdruid in #6630
• [HW] Make HWInstanceLike agnostic of the number of targets by @nandor in #6623
• [ESI] Simplify services by standardizing on to_client ports by @teqdruid in #6633
• [PyCDE] Adapt to new to_client style services by @teqdruid in #6634
• [PyCDE] Support ESI's FuncService by @teqdruid in #6636
• CMake: Fetch slang via git to workaround version check bug. by @dtzSiFive in #6640
• [FIRRTL] Prerequisites for Layer-Associated Probes by @seldridge in #6574
• [FIRRTL] Add enabled layers to FModuleOp by @seldridge in #6627

Full Changelog: firtool-1.64.0...firtool-1.65.0

firtool-1.64.0

What's Changed

• [FIRRTL] Create debug info scopes for inlined modules by @fabianschuiki in #6512
• [Seq][FIRRTL] Add a representation for clock inverters by @nandor in #6575
• [FIRRTL][ExtractInstances] Clear entire state on pass invocation by @fzi-hielscher in #6599
• [FIRRTL] Initial support for classes and objects in Dedup. by @mikeurbach in #6582
• [PyCDE] Fix import hw modules (#6130) by @teqdruid in #6605
• [HW to BTOR2] Add support for nested Wires and Compreg by @dobios in #6602
• [FIRRTL] CheckCombCycles ignores foriegn ops. by @darthscsi in #6612
• [NFC][FIRRTL] Canonicalize away empty probes by @nandor in #6617

Full Changelog: firtool-1.63.0...firtool-1.64.0

firtool-1.63.0

What's Changed

• [Sim] Introduce the rationale for the sim dialect by @nandor in #6536
• [Sim] Initial implementation of the sim dialect by @nandor in #6561
• [NFC] Fix warnings from missing include in ESI runtime. by @darthscsi in #6567
• [FIRRTL] Innocuous change to mitigate #6513 by @teqdruid in #6571
• [Arc] Use CallOp instead of latency 0 StateOp by @maerhart in #6560
• Bump LLVM by @darthscsi in #6566
• [NFC] try cleaner fix to windows issue by @darthscsi in #6573
• [FSM] Add CAPI dependency on conversion pass header generation. by @mikeurbach in #6572
• [Arc] StateOp: latency instead of lat in assembly format by @maerhart in #6562
• [Arc] Dedup: Fix use after free by @hovind in #6568
• [NFC] Convert getPortAttributes back to ArrayRef by @darthscsi in #6531
• [FIRRTL] Add Layer Association to Probes by @seldridge in #6551
• broken image src's fixed by @cap-oglu in #6578
• [FSMToSV][NFC] Correct pass summary by @TaoBi22 in #6580
• [ESI][Runtime] Add a utility to wrap a command with a cosimulation by @teqdruid in #6579
• [Builds] Revert back to small runners by @teqdruid in #6586
• [ESI] Introduce MMIO std service by @teqdruid in #6584
• [ESI] Lower manifest op to a ROM by @teqdruid in #6585
• [FIRRTL][CAPI] Expose foldFlow function by @SpriteOvO in #6577
• [PyCDE] Support for ESI MMIO service -- read side only by @teqdruid in #6590
• [FIRRTL] [LowerSignatures] Naming bounce wires properly by @uenoku in #6594
• [PyCDE] Fix service generator warning by @teqdruid in #6595
• [ESI] MMIO based manifest cosim support by @teqdruid in #6592
• [CombFolds] Flatten operands all at once by @uenoku in #6593
• bump llvm submodule to tip of main (103fa3250c46) by @mwachs5 in #6589
• [Comb] Handle type aliases in comb.concat by @hovind in #6588
• [CheckCombLoops] Refactor comb loop detection pass by @prithayan in #5647
• [ESI] XRT support for MMIO based manifest fetching by @teqdruid in #6596
• [PyCDE] Add ESI metadata to modules by @teqdruid in #6597

New Contributors

• @hovind made their first contribution in #6568
• @cap-oglu made their first contribution in #6578

Full Changelog: firtool-1.62.0...firtool-1.63.0

firtool-1.62.0

What's Changed

• [FIRRTL] Enable lowersigs and passive wires by @darthscsi in #6479
• [InstancePath] Add accessors to allow ops to reference multiple targets by @nandor in #6446
• [Debug] Make paths in HGLDD files relative by @fabianschuiki in #6451
• [Debug] Add scope op by @fabianschuiki in #6454
• [CombToArith] Fix lowering of concat with single operand by @fabianschuiki in #6505
• [Arc] Partially enable reset/enable detection by @fabianschuiki in #6506
• [Arc] Add support for struct and array states by @fabianschuiki in #6508
• [ESI] Fix pycde integration tests by @teqdruid in #6514
• [Scheduling] Define problem to model operator chaining in cyclic problem. by @leothaud in #6485
• [ESI] Fix pycde integration tests by @teqdruid in #6518
• [FIRRTL] Add options and instance choices by @nandor in #6504
• [SVExtractTestCode] Privatize generated modules by @uenoku in #6519
• [FIREmitter] Bump the version to 4.0.0 by @nandor in #6522
• [FIRRTL] Add a pass to specialize instance choices by @nandor in #6507
• [FIRRTL] Add a parser for firrtl.instance_choice by @nandor in #6509
• [Debug] Add inline scope support to HGLDD emission by @fabianschuiki in #6511
• [NFC] Make CHIRRTL more normal in preparation for moving some stuff in by @darthscsi in #6521
• [FIRRTL] Add an emitter for options and instance choices by @nandor in #6520
• [HW to BTOR2] btor2 conversion pass by @dobios in #6378
• [FIRRTL] Framework for intrinsic lowering by @nandor in #6527
• [LowerToHW] Fix output port index mapping by @prithayan in #6530
• [FIRRTL] Intrinsics: Fix lifetime issues in lambda. by @dtzSiFive in #6534
• [OM] Use type replacer to handle block arguments. by @mikeurbach in #6532
• [ModuleInliner] Donot retop a HierPathOp if flattening the root by @prithayan in #6515
• [LowerSignatures] Fix potential UAF by @uenoku in #6537
• [ESI][Runtime][NFC] Minor refactor and cleanup by @teqdruid in #6539
• [ESI][Runtime] Add design hierarchy printing to esiquery by @teqdruid in #6540
• [ESI][Runtime] Add type serialization support to Python bindings by @teqdruid in #6541
• [PyCDE] Fix ESI integration tests by @teqdruid in #6542
• [PyCDE] Fix ESI service implementations by @teqdruid in #6545
• [Support][FIRRTL] Debug Cleanup by @seldridge in #6546
• [CI] Fix release asset upload job permissions, support manual runs. by @dtzSiFive in #6547
• [CI] Bump runner for windows release artifacts 2019 -> 2022. by @dtzSiFive in #6548
• [LowerSignatures] Fix instance locations by @fabianschuiki in #6550
• [CI] Add option to control whether workflow_dispatch has asserts+debug. by @dtzSiFive in #6549
• [Docs] fix typos in Dialects/ by @shuoer86 in #6555
• [FIRRTL] Update InstanceGraph on erase in LowerClasses. by @mikeurbach in #6558
• [FIRRTL] Fix the lowering of internal paths in LowerSignatures by @nandor in #6556
• [HW][Seq] Select the better name when dropping wires and casts by @nandor in #6559
• [NFC] Bump LLVM over mnemonic change by @darthscsi in #6563

New Contributors

• @leothaud made their first contribution in #6485
• @shuoer86 made their first contribution in #6555

Full Changelog: firtool-1.61.0...firtool-1.62.0

Firtool 1.59.1 Release

What's Changed

• [LowerToHW] Pass through attributes on FModuleOp by @uenoku in #6400
• [LowerToHW] Fix output port index mapping by @prithayan in #6530

Full Changelog: firtool-1.59.0...firtool-1.59.1

Firtool 1.61.0 Release

What's Changed

• [HW] Fix getPortList to avoid n^2 location gathering. by @dtzSiFive in #6469
• [firtool] Fix missing option setter by @seldridge in #6470
• [FIRRTL] Create LowerSignatures to handle module signatures. by @darthscsi in #6359
• [ESI] Function call std service by @teqdruid in #6465
• [Python] Add debug dialect bindings by @fabianschuiki in #6471
• [ESI] Add std service name to manifest by @teqdruid in #6472
• [FIRRTL][CAPI] Add the rest of setters for options by @SpriteOvO in #6438
• [Debug] Add option to only mention existing files in HGLDD by @fabianschuiki in #6452
• [ESI][Runtime] Filling out the type system by @teqdruid in #6476
• [ESI][Runtime] Get build working on Windows by @teqdruid in #6478
• [FIRRTL] Passive Wires pass by @darthscsi in #6475
• [FIRRTL][NFC] Add clockgate instName to FirtoolOptions setters. by @prithayan in #6460
• [Arc] Add option to observe registers and memories by @fabianschuiki in #6477
• [OM] Update result type for EmptyPathOp. by @mikeurbach in #6481
• [NFC] Disable -misc-include-cleaner by @nandor in #6483
• [FIRRTL] Add helpers for the implementation of FIRRTL instance-like ops by @nandor in #6484
• [HardwareToHW]Fix wrong lowering of arith.shli by @HahaLan97 in #6487
• [Pipeline] Use Block::BlockArgListType to avoid const. by @dtzSiFive in #6489
• [FIRRTL][WireDFT] Wire test-en to ClockGateIntrinsic. by @dtzSiFive in #6488
• [ESI][Integration test] Fix requires and run commands by @teqdruid in #6480
• [FIRRTL][Parser] Improve rwprobe parsing, support inst results. by @dtzSiFive in #6258
• [FIRRTL][CAPI] Build open bundle for fields containing non-base types by @SpriteOvO in #6482
• Bump LLVM by @jackkoenig in #6494
• [FlattenIO] Fix module input and output port name order. by @prithayan in #6495
• [firtool] Add option to treat EICG_wrapper as intrinsic by @fabianschuiki in #6499
• [NFC][ESI] Refactor runtime headers and design hierarchy by @teqdruid in #6503
• [Arc] Use seq.clock_gate op by @fabianschuiki in #6501

New Contributors

• @HahaLan97 made their first contribution in #6487

Full Changelog: firtool-1.60.0...firtool-1.61.0