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Releases: llvm/circt

firtool-1.111.0

29 Mar 05:25
firtool-1.111.0
7669340
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Full Changelog: firtool-1.110.0...firtool-1.111.0

firtool-1.110.0

22 Mar 03:13
firtool-1.110.0
3f82acb
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  • [FIRRTL][AdvancedLayerSink] Add the ability to sink ops by cloning by @rwy7 in #8308
  • [AffineToSCF][Calyx] Lower Affine to SCF for Calyx by @jiahanxie353 in #8323
  • [LowerToBMC] Add comb as a dialect dependency by @TaoBi22 in #8326
  • [OM] Add missing CAPI omTypeIsAMapType by @unlsycn in #8321
  • [SCFToCalyx] If op with sequential condition by @jiahanxie353 in #7687
  • [LowerSMTToZ3LLVM] Change printf type provided to lookupOrCreateFn by @TaoBi22 in #8327
  • [FIRRTL] Canonicalize Assert(clk, p, e) when p == e by @rwy7 in #8320
  • [SV] Add preprocessor include op by @rwy7 in #8329
  • [circt-bmc] add rising clocks only mode by @TaoBi22 in #8330
  • [SMT] expand Z3 library check in integration tests by @TaoBi22 in #8333
  • [Python] Add binding for OutputFileAttr filename. by @mikeurbach in #8337
  • [verif] add booth contract example by @leonardt in #8319
  • [ExportVerilog] Back-annotate output file attributes during export. by @mikeurbach in #8338
  • Bump LLVM to 4d5a963eaf6ad209487a321dee7f0cd2a0f98477. by @mikeurbach in #8336

Full Changelog: firtool-1.109.0...firtool-1.110.0

firtool-1.109.0

10 Mar 06:08
231dea0
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Full Changelog: firtool-1.108.0...firtool-1.109.0

firtool-1.108.0

28 Feb 20:51
firtool-1.108.0
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  • [MemoryBanking] Should not overwrite banking factor/dimension when resolving attribute values by @jiahanxie353 in #8267
  • [LLHD] Add dedicated Mem2Reg pass by @fabianschuiki in #8244
  • [ESI][XRT] Implement "Indirect MMIO" by @teqdruid in #8273
  • [ImportVerilog] Add option to lower always @* as always_comb by @fabianschuiki in #8271
  • [LLHD] Support conditional drives in mem2reg by @fabianschuiki in #8278
  • [ESI][BSP] Simple ToHost DMA engine by @teqdruid in #8207
  • [LLHD] Support drives with delta delay in mem2reg by @fabianschuiki in #8279
  • [AffineParallelUnroll] Fix empty map lookup; move canonicalization passes before MemoryConflictResolver by @jiahanxie353 in #8282
  • [circt-verilog-lsp-server] Add Verilog Language Server by @uenoku in #8234
  • [SMT][CAPI] Add more SMT C API by @Clo91eaf in #8274
  • [MemoryBanking] Memory banking supports multiple banking factors/dimensions config by @jiahanxie353 in #8277
  • [Python] Declare a separate sub-target for support sources by @maerhart in #8243
  • [sim] Add emission for plusargs for UPF simulations by @youngar in #8272

Full Changelog: firtool-1.107.0...firtool-1.108.0

firtool-1.107.0

23 Feb 20:52
firtool-1.107.0
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Full Changelog: firtool-1.106.0...firtool-1.107.0

firtool-1.106.0

17 Feb 20:49
firtool-1.106.0
fa73e07
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Full Changelog: firtool-1.105.0...firtool-1.106.0

firtool-1.105.0

08 Feb 00:17
firtool-1.105.0
020bfc4
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Full Changelog: firtool-1.104.0...firtool-1.105.0

firtool-1.104.0

02 Feb 19:47
firtool-1.104.0
d47a9d2
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Full Changelog: firtool-1.103.0...firtool-1.104.0

firtool-1.103.0

24 Jan 21:57
firtool-1.103.0
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Full Changelog: firtool-1.102.0...firtool-1.103.0

firtool-1.102.0

21 Jan 22:06
77553d7
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  • Bump LLVM to ebc7efbab5c58b46f7215d63be6d0208cb588192. by @mikeurbach in #8089
  • [HW][circt-synth] Implement AggregateToComb pass and add to circt-synth pipeline by @uenoku in #8068
  • [SCFToCalyx] Wrap blocks with scf::ExecuteRegion when creating the new scf::Parallel by @jiahanxie353 in #8098
  • [Kanagawa] Remove %this by @mortbopet in #8097
  • [RTG][Elaboration] Move ConstantLike check after TypeSwitch for better performance by @maerhart in #7998
  • [ExtractInstances] Append original instance name to path in metadata by @prithayan in #7872

Full Changelog: firtool-1.101.0...firtool-1.102.0