RTL optimizations for Verilator#66

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MaxWipfli wants to merge 2 commits intopulp-platform:pulp-v1from

MaxWipfli:verilator_speedup

Commits on Jun 20, 2025

cva6_tlb_sv39x4: Replace (2 ** X) with (1 << X) for Verilator
MaxWipfli
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Commits on Jul 10, 2025

Add `ifndef to allow disabling instruction tracer
MaxWipfli
committed