Add support for multi-cycle response memory macros

[Scheremo]

This PR adds support for using multi-cycle response / pipeline-mode memory macros. Such macros typically have better C -> Q timing arcs at the cost of one cycle of additional reponse latency.

This PR depends on this PR, at least for testing of the feature on my end.

Added

• Parameter BankAccessLatency which configures how many clock cycles of latency each memory macro requires

Changed

• Updated verible config to enforce 100 character column limit

[micprog]

LGTM 👍