Add support for multi-cycle response memory macros

.verilog_format

@@ -1,7 +1,7 @@
 --column_limit=100
 --indentation_spaces=2
 --line_break_penalty=2
---over_column_limit_penalty=10000
+--over_column_limit_penalty=100
 --wrap_spaces=4
 --assignment_statement_alignment=align
 --case_items_alignment=align
@@ -18,7 +18,7 @@
 --port_declarations_alignment=align
 --port_declarations_indentation=indent
 --struct_union_members_alignment=align
---try_wrap_long_lines=false
+--try_wrap_long_lines=true
 --wrap_end_else_clauses=false
 --port_declarations_right_align_packed_dimensions=false
 --port_declarations_right_align_unpacked_dimensions=false

Bender.yml

@@ -6,6 +6,7 @@ package:
   name: memory_island
   authors:
     - "Michael Rogenmoser <[email protected]>"
+    - "Moritz Scherer <[email protected]>"
 
 dependencies:
   common_cells:         { git: "https://github.com/pulp-platform/common_cells.git",         version: 1.37.0 }

src/axi_memory_island_wrap.sv

@@ -3,6 +3,7 @@
 // SPDX-License-Identifier: SHL-0.51
 
 // Michael Rogenmoser <[email protected]>
+// Moritz Scherer <[email protected]>
 
 module axi_memory_island_wrap #(
   /// Address Width
@@ -51,13 +52,15 @@ module axi_memory_island_wrap #(
   parameter int unsigned WidePriorityWait = 1,
 
   /// Banking Factor for the Wide Ports (power of 2)
-  parameter int unsigned NumWideBanks  = (1 << $clog2(NumWideReq)) * 2 * 2,
+  parameter int unsigned NumWideBanks      = (1 << $clog2(NumWideReq)) * 2 * 2,
   /// Extra multiplier for the Narrow banking factor (baseline is WideWidth/NarrowWidth) (power of 2)
-  parameter int unsigned NarrowExtraBF = 1,
+  parameter int unsigned NarrowExtraBF     = 1,
   /// Words per memory bank. (Total number of banks is (WideWidth/NarrowWidth)*NumWideBanks)
-  parameter int unsigned WordsPerBank  = 1024,
+  parameter int unsigned WordsPerBank      = 1024,
   // verilog_lint: waive explicit-parameter-storage-type
-  parameter              MemorySimInit = "none"
+  parameter              MemorySimInit     = "none",
+  /// Number of cycles a memory macro takes to respond to a read request
+  parameter int unsigned BankAccessLatency = 1
 ) (
   input logic clk_i,
   input logic rst_ni,
@@ -68,29 +71,19 @@ module axi_memory_island_wrap #(
   input  axi_wide_req_t [NumWideReq-1:0] axi_wide_req_i,
   output axi_wide_rsp_t [NumWideReq-1:0] axi_wide_rsp_o
 );
-
+  localparam int unsigned NWDivisor = WideDataWidth / NarrowDataWidth;
+  localparam int unsigned BankAddrMemWidth = $clog2(WordsPerBank);
   localparam int unsigned NarrowStrbWidth = NarrowDataWidth / 8;
   localparam int unsigned WideStrbWidth = WideDataWidth / 8;
 
   localparam int unsigned InternalNumNarrow = NumNarrowReq + $countones(NarrowRW);
   localparam int unsigned InternalNumWide = NumWideReq + $countones(WideRW);
 
-  localparam int unsigned NarrowMemRspLatency = SpillNarrowReqEntry +
-                                                SpillNarrowReqRouted +
-                                                SpillReqBank +
-                                                SpillRspBank +
-                                                SpillNarrowRspRouted +
-                                                SpillNarrowRspEntry +
-                                                1;
-  localparam int unsigned  WideMemRspLatency = SpillWideReqEntry +
-                                               SpillWideReqRouted +
-                                               SpillWideReqSplit +
-                                               SpillReqBank +
-                                               SpillRspBank +
-                                               SpillWideRspSplit +
-                                               SpillWideRspRouted +
-                                               SpillWideRspEntry +
-                                               1;
+  localparam int unsigned NarrowMemRspLatency = SpillNarrowReqEntry + SpillNarrowReqRouted +
+      SpillReqBank + SpillRspBank + SpillNarrowRspRouted + SpillNarrowRspEntry + BankAccessLatency;
+  localparam int unsigned WideMemRspLatency = SpillWideReqEntry + SpillWideReqRouted +
+      SpillWideReqSplit + SpillReqBank + SpillRspBank + SpillWideRspSplit + SpillWideRspRouted +
+      SpillWideRspEntry + BankAccessLatency;
 
   logic [InternalNumNarrow-1:0]                      narrow_req;
   logic [InternalNumNarrow-1:0]                      narrow_gnt;
@@ -206,7 +199,7 @@ module axi_memory_island_wrap #(
         .axi_req_t   (axi_wide_req_t),
         .axi_resp_t  (axi_wide_rsp_t),
         .AddrWidth   (AddrWidth),
-        .AxiDataWidth(WideDataWidth),
+        .DataWidth   (WideDataWidth),
         .IdWidth     (AxiWideIdWidth),
         .NumBanks    (1),
         .BufDepth    (1 + WideMemRspLatency),
@@ -254,7 +247,8 @@ module axi_memory_island_wrap #(
     .SpillReqBank        (SpillReqBank),
     .SpillRspBank        (SpillRspBank),
     .WidePriorityWait    (WidePriorityWait),
-    .MemorySimInit       (MemorySimInit)
+    .MemorySimInit       (MemorySimInit),
+    .BankAccessLatency   (BankAccessLatency)
   ) i_memory_island (
     .clk_i,
     .rst_ni,

src/memory_island_core.sv

@@ -3,6 +3,7 @@
 // SPDX-License-Identifier: SHL-0.51
 
 // Michael Rogenmoser <[email protected]>
+// Moritz Scherer <[email protected]>
 
 module memory_island_core #(
   /// Address Width
@@ -47,9 +48,11 @@ module memory_island_core #(
   parameter int unsigned WidePriorityWait = 1,
 
   // Derived, DO NOT OVERRIDE
-  parameter int unsigned NarrowStrbWidth = NarrowDataWidth / 8,
-  parameter int unsigned WideStrbWidth   = WideDataWidth / 8,
-  parameter int unsigned NWDivisor       = WideDataWidth / NarrowDataWidth
+  parameter int unsigned NarrowStrbWidth   = NarrowDataWidth / 8,
+  parameter int unsigned WideStrbWidth     = WideDataWidth / 8,
+  parameter int unsigned NWDivisor         = WideDataWidth / NarrowDataWidth,
+  parameter int unsigned BankAddrMemWidth  = $clog2(WordsPerBank),
+  parameter int unsigned BankAccessLatency = 1
 ) (
   input logic clk_i,
   input logic rst_ni,
@@ -73,6 +76,7 @@ module memory_island_core #(
   input  logic [NumWideReq-1:0][WideStrbWidth-1:0] wide_strb_i,
   output logic [NumWideReq-1:0]                    wide_rvalid_o,
   output logic [NumWideReq-1:0][WideDataWidth-1:0] wide_rdata_o
+
 );
 
   initial begin
@@ -100,19 +104,15 @@ module memory_island_core #(
   localparam int unsigned AddrNarrowWordBit = $clog2(NarrowDataWidth / 8);
   localparam int unsigned AddrWideWordBit = $clog2(WideDataWidth / 8);
   localparam int unsigned AddrNarrowWideBit = AddrWideWordBit + $clog2(NarrowExtraBF);
+
   localparam int unsigned AddrWideBankBit = AddrWideWordBit + $clog2(NumWideBanks);
   localparam int unsigned AddrTopBit = AddrWideBankBit + $clog2(WordsPerBank);
 
   localparam int unsigned NarrowAddrMemWidth = AddrTopBit - AddrNarrowWideBit;
-  localparam int unsigned BankAddrMemWidth = $clog2(WordsPerBank);
 
-  localparam int unsigned NarrowIntcBankLat = 1 +
-                                              SpillNarrowReqRouted +
-                                              SpillNarrowRspRouted +
-                                              SpillReqBank +
-                                              SpillRspBank;
 
-  localparam int unsigned PriorityWaitWidth = cf_math_pkg::idx_width(WidePriorityWait);
+  localparam int unsigned NarrowIntcBankLat = BankAccessLatency + SpillNarrowReqRouted +
+      SpillNarrowRspRouted + SpillReqBank + SpillRspBank;
 
   logic [NumNarrowReq-1:0] narrow_req_entry_spill;
   logic [NumNarrowReq-1:0] narrow_gnt_entry_spill;
@@ -209,7 +209,8 @@ module memory_island_core #(
   logic [NumWideBanks-1:0][NWDivisor-1:0][NarrowDataWidth-1:0] rdata_bank_spill;
 
   logic [NumWideBanks-1:0][NWDivisor-1:0] narrow_priority_req;
-  logic [NumWideBanks-1:0][NWDivisor-1:0][PriorityWaitWidth-1:0] wide_priority_d, wide_priority_q;
+  logic [NumWideBanks-1:0][NWDivisor-1:0][cf_math_pkg::idx_width(WidePriorityWait)-1:0]
+      wide_priority_d, wide_priority_q;
 
   for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_entry_cuts
     mem_req_multicut #(
@@ -382,7 +383,7 @@ module memory_island_core #(
           for (int wideBank = 0; wideBank < TotalBanks / WidePseudoBanks; wideBank++) begin
             if (narrow_addr_routed_spill[PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank) begin
               narrow_gnt_routed_spill[PseudoIdx] =
-                narrow_gnt_bank [(wideBank*NarrowExtraBF)+extraFactor][subBank];
+                  narrow_gnt_bank[(wideBank*NarrowExtraBF)+extraFactor][subBank];
             end
           end
         end
@@ -400,10 +401,10 @@ module memory_island_core #(
       for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_l3
         localparam int unsigned WideBankIdx = (wideBank * NarrowExtraBF) + extraFactor;
         localparam int unsigned PseudoIdx = (extraFactor * NWDivisor) + subBank;
-        assign narrow_req_bank  [WideBankIdx][subBank] = narrow_req_routed_spill  [PseudoIdx] &
-          (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank);
-        assign narrow_addr_bank [WideBankIdx][subBank] =
-          narrow_addr_routed_spill [PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth];
+        assign narrow_req_bank[WideBankIdx][subBank] = narrow_req_routed_spill[PseudoIdx] &
+            (narrow_addr_routed_spill[PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank);
+        assign narrow_addr_bank[WideBankIdx][subBank] =
+            narrow_addr_routed_spill[PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth];
         assign narrow_we_bank[WideBankIdx][subBank] = narrow_we_routed_spill[PseudoIdx];
         assign narrow_wdata_bank[WideBankIdx][subBank] = narrow_wdata_routed_spill[PseudoIdx];
         assign narrow_strb_bank[WideBankIdx][subBank] = narrow_strb_routed_spill[PseudoIdx];
@@ -428,7 +429,7 @@ module memory_island_core #(
         .d_o(narrow_rdata_sel)
       );
       assign narrow_rdata_routed_spill[PseudoIdx] =
-        narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF) + extraFactor][subBank];
+          narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF)+extraFactor][subBank];
     end
   end
 
@@ -615,14 +616,14 @@ module memory_island_core #(
       assign req_bank[i][j] = narrow_req_bank[i][j] | wide_req_bank_spill[i][j];
       assign narrow_gnt_bank[i][j] = narrow_priority_req[i][j];
       assign wide_gnt_bank_spill[i][j] = ~narrow_priority_req[i][j];
-      assign we_bank              [i][j] =  narrow_priority_req[i][j] ? narrow_we_bank       [i][j]:
-                                                                        wide_we_bank_spill   [i][j];
-      assign addr_bank            [i][j] =  narrow_priority_req[i][j] ? narrow_addr_bank     [i][j]:
-                                                                        wide_addr_bank_spill [i][j];
-      assign wdata_bank           [i][j] =  narrow_priority_req[i][j] ? narrow_wdata_bank    [i][j]:
-                                                                        wide_wdata_bank_spill[i][j];
-      assign strb_bank            [i][j] =  narrow_priority_req[i][j] ? narrow_strb_bank     [i][j]:
-                                                                        wide_strb_bank_spill [i][j];
+      assign we_bank[i][j] = narrow_priority_req[i][j] ? narrow_we_bank[i][j] :
+          wide_we_bank_spill[i][j];
+      assign addr_bank[i][j] = narrow_priority_req[i][j] ? narrow_addr_bank[i][j] :
+          wide_addr_bank_spill[i][j];
+      assign wdata_bank[i][j] = narrow_priority_req[i][j] ? narrow_wdata_bank[i][j] :
+          wide_wdata_bank_spill[i][j];
+      assign strb_bank[i][j] = narrow_priority_req[i][j] ? narrow_strb_bank[i][j] :
+          wide_strb_bank_spill[i][j];
       assign narrow_rdata_bank[i][j] = rdata_bank[i][j];
       assign wide_rdata_bank_spill[i][j] = rdata_bank[i][j];
 
@@ -671,7 +672,7 @@ module memory_island_core #(
         .DataWidth(NarrowDataWidth),
         .ByteWidth(8),
         .NumPorts (1),
-        .Latency  (1),
+        .Latency  (BankAccessLatency),
         .SimInit  (MemorySimInit)
       ) i_bank (
         .clk_i,
@@ -685,15 +686,18 @@ module memory_island_core #(
       );
 
       // Shift reg for wide rvalid
-      logic [SpillReqBank+SpillRspBank:0] shift_rvalid_d, shift_rvalid_q;
-      for (genvar k = 0; k < SpillReqBank + SpillRspBank + 1; k++) begin : gen_shift_rvalid
+      logic [SpillReqBank+SpillRspBank+BankAccessLatency-1:0] shift_rvalid_d, shift_rvalid_q;
+      for (
+          genvar k = 0; k < SpillReqBank + SpillRspBank + BankAccessLatency; k++
+      ) begin : gen_shift_rvalid
         if (k == 0) begin : gen_shift_in
           assign shift_rvalid_d[k] = req_bank[i][j] & wide_gnt_bank[i][j];
         end else begin : gen_shift
           assign shift_rvalid_d[k] = shift_rvalid_q[k-1];
         end
       end
-      assign wide_rvalid_bank_spill[i][j] = shift_rvalid_q[SpillReqBank+SpillRspBank];
+      assign wide_rvalid_bank_spill[i][j] =
+          shift_rvalid_q[SpillReqBank+SpillRspBank+BankAccessLatency-1];
 
       always_ff @(posedge clk_i or negedge rst_ni) begin : proc_wide_bank_rvalid
         if (~rst_ni) begin

src/stream_mem_to_banks_det.sv

@@ -152,10 +152,10 @@ module stream_mem_to_banks_det #(
     assign zero_strobe[i]  = (|bank_req[i].strb == '0);
 
     if (HideStrb) begin : gen_hide_strb
-      assign bank_req_o[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ?
-                               1'b0 : bank_req_internal[i];
-      assign bank_gnt_internal[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ?
-                                      1'b1 : bank_gnt_i[i];
+      assign bank_req_o[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? 1'b0 :
+          bank_req_internal[i];
+      assign bank_gnt_internal[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? 1'b1 :
+          bank_gnt_i[i];
     end else begin : gen_legacy_strb
       assign bank_req_o[i]        = bank_req_internal[i];
       assign bank_gnt_internal[i] = bank_gnt_i[i];

src/varlat_inorder_interco.sv

@@ -137,9 +137,8 @@ module varlat_inorder_interco #(
 
     // Response path
     for (genvar i = 0; i < NumIn; i++) begin : gen_rsp
-      assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] &
-                        rready_o[bank_sel_rsp[i]] &
-                        (ini_addr_rsp[bank_sel_rsp[i]] == i);
+      assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] & rready_o[bank_sel_rsp[i]] &
+          (ini_addr_rsp[bank_sel_rsp[i]] == i);
       assign rdata_o[i] = rdata_i[bank_sel_rsp[i]];
     end
     for (genvar i = 0; i < NumOut; i++) begin : gen_rready