Add Zilsd/Zclsd support

coverage/dataset.cgf

@@ -171,6 +171,24 @@ datasets:
     x28: 0
     x30: 0
 
+  pair_regs_zilsd: &pair_regs_zilsd
+    x0: 0
+    x2: 0
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   c_regs: &c_regs
     x8: 0
     x9: 0
@@ -256,6 +274,28 @@ datasets:
     x30: 0
     x31: 0
 
+  c_pair_regs: &c_pair_regs
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+
+  c_pair_regs_mx2: &c_pair_regs_mx2
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   cbfmt_immval_sgn: &cbfmt_immval_sgn
     'imm_val == (-2**(6-1))': 0
     'imm_val == 0': 0

coverage/zilsd/rv32zilsd.cgf

@@ -0,0 +1,128 @@
+# See License https://gitlab.com/vyoma_systems/common/-/blob/main/LICENSE.BSD3.vyoma for more details
+
+ld:
+    config: 
+      - check ISA:=regex(.*I.*Zilsd.*)
+    opcode: 
+      ldz: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *pair_regs_zilsd
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+        'ea_align == 0 and (imm_val % 8) == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 1': 0
+        'ea_align == 0 and (imm_val % 8) == 2': 0
+        'ea_align == 0 and (imm_val % 8) == 3': 0
+        'ea_align == 0 and (imm_val % 8) == 4': 0
+        'ea_align == 0 and (imm_val % 8) == 5': 0
+        'ea_align == 0 and (imm_val % 8) == 6': 0
+        'ea_align == 0 and (imm_val % 8) == 7': 0
+        'imm_val > 0': 0
+        'imm_val < 0': 0
+        'imm_val == 0': 0       
+
+
+sd:
+    config: 
+      - check ISA:=regex(.*I.*Zilsd.*)
+    opcode: 
+      sdz: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *pair_regs_zilsd
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0 and (imm_val % 8) == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 1': 0
+        'ea_align == 0 and (imm_val % 8) == 2': 0
+        'ea_align == 0 and (imm_val % 8) == 3': 0
+        'ea_align == 0 and (imm_val % 8) == 4': 0
+        'ea_align == 0 and (imm_val % 8) == 5': 0
+        'ea_align == 0 and (imm_val % 8) == 6': 0
+        'ea_align == 0 and (imm_val % 8) == 7': 0
+        'imm_val > 0': 0
+        'imm_val < 0': 0
+        'imm_val == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+
+
+
+cldsp:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.ldspz: 0
+    rd: 
+      <<: *pair_regs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0
+
+csdsp:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.sdspz: 0
+    rs2: 
+      <<: *pair_regs_zilsd
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0
+
+cld:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.ldz: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_pair_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+csd:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.sdz: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_pair_regs
+    op_comb:
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0

coverage/zilsd/rv32zilsd_priv.cgf

@@ -0,0 +1,39 @@
+misalign-sd:
+  config:
+    - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True
+    - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
+  cond: check ISA:=regex(.*32.*I.*Zicsr.*)
+  mnemonics:
+    sdz: 0
+  rs1: 
+    <<: *all_regs_mx0
+  rs2: 
+    <<: *pair_regs_zilsd
+  val_comb:
+    'ea_align == 1': 0
+    'ea_align == 2': 0
+    'ea_align == 3': 0
+    'ea_align == 4': 0
+    'ea_align == 5': 0
+    'ea_align == 6': 0
+    'ea_align == 7': 0
+
+misalign-ld:
+  config:
+    - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True
+    - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
+  cond: check ISA:=regex(.*32.*I.*Zicsr.*)
+  mnemonics:
+    ldz: 0
+  rs1: 
+    <<: *all_regs_mx0
+  rd: 
+    <<: *pair_regs_zilsd
+  val_comb:
+    'ea_align == 1': 0
+    'ea_align == 2': 0
+    'ea_align == 3': 0
+    'ea_align == 4': 0
+    'ea_align == 5': 0
+    'ea_align == 6': 0
+    'ea_align == 7': 0

riscv-ctg/riscv_ctg/constants.py

@@ -193,7 +193,7 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 # increment each value in dataset, increment each value in dataset, add them to the dataset
     return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0
 
-template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml"]
+template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml","zilsd.yaml"]
 
 template_files = [os.path.join(root,"data/"+f) for f in template_fnames]
 

riscv-ctg/riscv_ctg/data/template.yaml

@@ -7,6 +7,9 @@ metadata:
   c_fregs: &c_fregs "['x'+str(x) for x in range(8,16)]"
   pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
   rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]"
+  pair_regs_zclsd: &pair_regs_zclsd "['x'+str(x) for x in range(2,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  pair_regs_zilsd: &pair_regs_zilsd "['x'+str(x) for x in range(0,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  c_pair_regs: &c_pair_regs "['x'+str(x) for x in range(8,16,2)]"
 
 aes32dsi:
   sig:

riscv-ctg/riscv_ctg/data/zilsd.yaml

@@ -0,0 +1,128 @@
+# See https://gitlab.com/vyoma_systems/common/-/blob/main/LICENSE.BSD3.vyoma for more details
+ldz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *pair_regs_zilsd
+  rd_hi: 0
+  isa: 
+    - IZilsd
+  xlen: [32]
+  opcode: ld
+  std_op:
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode:$opcode op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align;rd_hi:$rd_hi
+    TEST_LOAD_ZILSD($swreg,$testreg,$index,$rs1,$rd,$rd_hi,$imm_val,$offset,ld,$ea_align)
+
+sdz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *pair_regs_zilsd
+  rd_op_data: *all_regs
+  rs2_hi: 0
+  xlen: [32]
+  opcode: sd
+  std_op:
+  isa: 
+    - IZilsd
+  formattype: 'szformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  rs2_hi_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode:$opcode; op1:$rs1; op2:$rs2; op2val:$rs2_val;op3val:$rs2_hi_val; immval:$imm_val; align:$ea_align; rs2_hi:$rs2_hi
+    TEST_STORE_ZILSD($swreg,$testreg,$index,$rs1,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,sd,$ea_align)
+
+c.ldz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rd_op_data: *c_pair_regs 
+  rd_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zclsd
+  formattype: 'clformat'
+  rs1_val_data: '[0]'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val; rd_hi:$rd_hi
+    TEST_LOAD_ZILSD($swreg,$testreg,$index,$rs1,$rd,$rd_hi,$imm_val,$offset,c.ld,$rs1_val)
+
+c.ldspz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rd_op_data: *pair_regs_zclsd
+  rd_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zclsd
+  formattype: 'ciformat'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; rd_hi:$rd_hi
+    TEST_LOAD_ZILSD($swreg,$testreg,$index,x2,$rd,$rd_hi,$imm_val,$offset,c.ldsp,0)
+
+c.sdz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_pair_regs
+  rs2_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zclsd
+  formattype: 'cszformat'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  rs2_hi_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; op3val:$rs2_hi_val; $immval:$imm_val; rs2_hi:$rs2_hi
+    TEST_STORE_ZILSD($swreg,$testreg,$index,$rs1,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,c.sd,0)
+
+c.sdspz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs2_op_data: *pair_regs_zilsd
+  rs2_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zclsd
+  formattype: 'csszformat'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  rs2_hi_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val;  op3val:$rs2_hi_val; immval:$imm_val; rs2_hi:$rs2_hi
+    TEST_STORE_ZILSD($swreg,$testreg,$index,x2,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,c.sdsp,0)

riscv-ctg/riscv_ctg/dsp_function.py

@@ -151,6 +151,12 @@ def incr_reg_num(reg):
     num = num + 1
     return name + str(num)
 
+def dec_reg_num(reg):
+    name = reg[0]
+    num = int(reg[1:])
+    num = num - 2
+    return name + str(num)
+
 def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile):
     '''
     This function generate high registers for paired register operands, rs1_hi, rs2_hi and rd_hi depending on the specification of the p64_profile string.