RVY encodings matching latest 0.9.9 draft

arg_lut.csv

@@ -92,6 +92,7 @@
 "rd_n2", 11, 7
 "rd_n0", 11, 7
 "rs1_n0", 11, 7
+"rs2_n0", 24, 20
 "c_rs2_n0", 6, 2
 "c_rs1_n0", 11, 7
 "c_rs2", 6, 2
@@ -113,3 +114,4 @@
 "p_rd_p", 11, 8
 "p_rs1_p", 19, 16
 "p_rs2_p", 24, 21
+"ybndswimm9", 28, 20

csrs.csv

@@ -93,6 +93,10 @@
 0x257, "vsireg6"
 0x25C, "vstopei"
 0x280, "vsatp"
+0x480, "utidc"
+0x580, "stidc"
+0x780, "mtidc"
+0xA80, "vstidc"
 0x600, "hstatus"
 0x602, "hedeleg"
 0x603, "hideleg"
@@ -246,6 +250,7 @@
 0x3ed, "pmpaddr61"
 0x3ee, "pmpaddr62"
 0x3ef, "pmpaddr63"
+0x416, "ddc"
 0x747, "mseccfg"
 0x7a0, "tselect"
 0x7a1, "tdata1"
@@ -259,6 +264,9 @@
 0x7b1, "dpc"
 0x7b2, "dscratch0"
 0x7b3, "dscratch1"
+0x7ba, "drootcsel"
+0x7bc, "dddc"
+0x7bd, "drootc"
 0xB00, "mcycle"
 0xB02, "minstret"
 0xB03, "mhpmcounter3"

extensions/unratified/rv32_y

@@ -0,0 +1,2 @@
+# 32-bit YHIR pseudo-op
+$pseudo_op rv_y::srliy  yhir    rd rs1 31..27=0 26..20=32 14..12=5 6..2=0x1E 1..0=3

extensions/unratified/rv32_y_c

@@ -0,0 +1,10 @@
+# When the base ISA is RV32Y, the Zcf instructions are remapped loads/stores of capabilities:
+#   c.ly:   repurposes c.flw
+#   c.sy:   repurposes c.fsw
+#   c.lysp: repurposes c.flwsp
+#   c.sysp: repurposes c.fswsp
+
+c.ly_rv32         rd_p rs1_p c_uimm8lo c_uimm8hi   1..0=0 15..13=3
+c.sy_rv32         rs1_p rs2_p c_uimm8hi c_uimm8lo  1..0=0 15..13=7
+c.lysp_rv32       rd_n0 c_uimm9sphi c_uimm9splo    1..0=2 15..13=3
+c.sysp_rv32       c_rs2 c_uimm9sp_s                1..0=2 15..13=7

extensions/unratified/rv64_y

@@ -0,0 +1,2 @@
+# 64-bit YHIR pseudo-op
+$pseudo_op rv_y::srliy  yhir    rd rs1 31..27=0 26..20=64 14..12=5 6..2=0x1E 1..0=3

extensions/unratified/rv64_y_c

@@ -0,0 +1,10 @@
+# When the base ISA is RV64Y, the Zcd instructions are remapped loads/stores of capabilities:
+#   c.ly:   repurposes c.fld
+#   c.sy:   repurposes c.fsd
+#   c.lysp: repurposes c.fldsp
+#   c.sysp: repurposes c.fsdsp
+
+c.ly_rv64         rd_p rs1_p c_uimm9lo c_uimm9hi     1..0=0 15..13=1
+c.sy_rv64         rs1_p rs2_p c_uimm9hi c_uimm9lo    1..0=0 15..13=5
+c.lysp_rv64       rd_n0 c_uimm10sphi c_uimm10splo    1..0=2 15..13=1
+c.sysp_rv64       c_rs2 c_uimm10sp_s                 1..0=2 15..13=5

extensions/unratified/rv64_y_zba

@@ -0,0 +1,6 @@
+# Operand Types: rd YLEN, rs1 XLEN, rs2 YLEN (0b101)
+ysh4add           rd rs1 rs2         31..25=0b0011_101 14..12=0 6..2=0x1E 1..0=3
+ysh1add.uw        rd rs1 rs2         31..25=0b0100_101 14..12=0 6..2=0x1E 1..0=3
+ysh2add.uw        rd rs1 rs2         31..25=0b0101_101 14..12=0 6..2=0x1E 1..0=3
+ysh3add.uw        rd rs1 rs2         31..25=0b0110_101 14..12=0 6..2=0x1E 1..0=3
+ysh4add.uw        rd rs1 rs2         31..25=0b0111_101 14..12=0 6..2=0x1E 1..0=3

extensions/unratified/rv_y

@@ -0,0 +1,48 @@
+# R-Type Instructions
+#
+# The lower 3 bits of funct7 [27:25] are a bitmask indicating YLEN (capability) operands:
+#   bit 25: rd (0 = XLEN, 1 = YLEN)
+#   bit 26: rs1 (0 = XLEN, 1 = YLEN)
+#   bit 27: rs2 (0 = XLEN, 1 = YLEN)
+
+# Operand Types: rd YLEN, rs1 XLEN, rs2 XLEN (0b001)
+packy                           rd rs1 rs2                31..25=0b0000_001 14..12=0 6..2=0x1E 1..0=3
+$pseudo_op rv_y::packy yhiw     rd rs1 rs2                31..25=0b0000_001 14..12=0 6..2=0x1E 1..0=3
+
+# Operand Types: rd YLEN, rs1 YLEN, rs2 XLEN (0b011)
+yadd                            rd rs1 rs2_n0             31..25=0b0000_011 14..12=0 6..2=0x1E 1..0=3
+ymv                             rd rs1                    31..25=0b0000_011 24..20=0 14..12=0 6..2=0x1E 1..0=3
+yaddrw                          rd rs1 rs2                31..25=0b0001_011 14..12=0 6..2=0x1E 1..0=3
+ypermc                          rd rs1 rs2                31..25=0b0010_011 14..12=0 6..2=0x1E 1..0=3
+ybndsw                          rd rs1 rs2                31..25=0b0011_011 14..12=0 6..2=0x1E 1..0=3
+ybndsrw                         rd rs1 rs2                31..25=0b0100_011 14..12=0 6..2=0x1E 1..0=3
+
+# Operand Types: rd XLEN, rs1 YLEN, rs2 YLEN (0b110)
+yeq                             rd rs1 rs2                31..25=0b0000_110 14..12=0 6..2=0x1E 1..0=3
+yss                             rd rs1 rs2                31..25=0b0001_110 14..12=0 6..2=0x1E 1..0=3
+
+# Operand Types: rd YLEN, rs1 YLEN, rs2 YLEN (0b111)
+ysunseal                        rd rs1 rs2                31..25=0b0000_111 14..12=0 6..2=0x1E 1..0=3
+ybld                            rd rs1 rs2                31..25=0b0001_111 14..12=0 6..2=0x1E 1..0=3
+#rs1 is in the format, but must be zero for now (non-zero will be yseal)
+ysentry                         rd rs2 19..15=0           31..25=0b0010_111 14..12=0 6..2=0x1E 1..0=3
+
+# 2-OP Instructions (encoded as R-type with using 1111 in the upper bits of funct7 and rs2=funct5)
+# Operand Types: rd XLEN, rs1 XLEN, rs2 N/A (0b000)
+yamask                          rd rs1                    31..25=0b1111_000 24..20=0 14..12=0 6..2=0x1E 1..0=3
+# Operand Types: rd XLEN, rs1 YLEN, rs2 N/A (0b010)
+ybaser                          rd rs1                    31..25=0b1111_010 24..20=0 14..12=0 6..2=0x1E 1..0=3
+ypermr                          rd rs1                    31..25=0b1111_010 24..20=1 14..12=0 6..2=0x1E 1..0=3
+ytopr                           rd rs1                    31..25=0b1111_010 24..20=2 14..12=0 6..2=0x1E 1..0=3
+ylenr                           rd rs1                    31..25=0b1111_010 24..20=3 14..12=0 6..2=0x1E 1..0=3
+ytagr                           rd rs1                    31..25=0b1111_010 24..20=4 14..12=0 6..2=0x1E 1..0=3
+ytyper                          rd rs1                    31..25=0b1111_010 24..20=5 14..12=0 6..2=0x1E 1..0=3
+
+# I-Type / S-Type Instructions
+yaddi                           rd rs1 imm12              14..12=4 6..2=0x1E 1..0=3
+ly                              rd rs1 imm12              14..12=1 6..2=0x1E 1..0=3
+sy                              imm12hi rs1 rs2 imm12lo   14..12=2 6..2=0x1E 1..0=3
+
+# MISC Instructions
+ybndswi                         rd rs1 ybndswimm9         31..29=0b111 14..12=5 6..2=0x1E 1..0=3
+srliy                           rd rs1 shamtq             31..27=0b00000 14..12=5 6..2=0x1E 1..0=3

extensions/unratified/rv_y_a

@@ -0,0 +1,3 @@
+lr.y              rd rs1 aq rl       31..27=0b00010 24..20=0 14..12=3 6..2=0x1E 1..0=3
+sc.y              rd rs1 rs2 aq rl   31..27=0b00011 14..12=3 6..2=0x1E 1..0=3
+amoswap.y         rd rs1 rs2 aq rl   31..27=0b00001 14..12=3 6..2=0x1E 1..0=3

extensions/unratified/rv_y_c

@@ -0,0 +1,2 @@
+# When the base ISA is RVY, c.mv is remapped to c.ymv to copy YLEN-wide values
+c.ymv rd_n0 c_rs2_n0                      1..0=2 15..13=4 12=0

extensions/unratified/rv_y_zba

@@ -0,0 +1,4 @@
+# Operand Types: rd YLEN, rs1 XLEN, rs2 YLEN (0b101)
+ysh1add           rd rs1 rs2         31..25=0b0000_101 14..12=0 6..2=0x1E 1..0=3
+ysh2add           rd rs1 rs2         31..25=0b0001_101 14..12=0 6..2=0x1E 1..0=3
+ysh3add           rd rs1 rs2         31..25=0b0010_101 14..12=0 6..2=0x1E 1..0=3

extensions/unratified/rv_zabhlrsc

@@ -0,0 +1,4 @@
+lr.b        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=0 6..2=0x0B 1..0=3
+lr.h        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=1 6..2=0x0B 1..0=3
+sc.b        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=0 6..2=0x0B 1..0=3
+sc.h        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=1 6..2=0x0B 1..0=3

extensions/unratified/rv_zyhybrid

@@ -0,0 +1,8 @@
+# Operand Types: rd YLEN, rs1 YLEN, rs2 XLEN (0b011)
+ymodew            rd_n0 rs1 rs2      31..25=0b0101_011 14..12=0 6..2=0x1E 1..0=3
+# Encoded as ymodew with rd=x0, using rs2 as funct5
+ymodeswi                             31..25=0b0101_011 24..20=1 19..15=0 14..12=0 11..7=0 6..2=0x1E 1..0=3
+ymodeswy                             31..25=0b0101_011 24..15=0 14..12=0 11..7=0 6..2=0x1E 1..0=3
+
+# Operand Types: rd XLEN, rs1 YLEN, rs2 N/A (0b010)
+ymoder            rd rs1             31..25=0b1111_010 24..20=6 14..12=0 6..2=0x1E 1..0=3

src/riscv_opcodes/constants.py

@@ -5,20 +5,25 @@
 
 # TODO: The constants in this file should be in all caps.
 overlapping_extensions = {
-    "rv_zcmt": {"rv_c_d"},
-    "rv_zcmp": {"rv_c_d"},
+    "rv_zcmt": {"rv_c_d", "rv64_y_c"},
+    "rv_zcmp": {"rv_c_d", "rv64_y_c"},
     "rv_c": {"rv_zcmop"},
     "rv64_p": {"rv32_p", "rv64_zbp"},
     "rv32_p": {"rv64_p", "rv_zcmt", "rv_c_d"},
     "rv_p": {"rv_zbb"},
+    "rv32_y_c": {"rv32_c_f", "rv32_zclsd"},
+    "rv64_y_c": {"rv_c_d"},
 }
 
 overlapping_instructions = {
     "c_addi": {"c_nop"},
     "c_lui": {"c_addi16sp"},
-    "c_mv": {"c_jr"},
+    "c_mv": {"c_jr", "c_ymv"},
+    "c_ymv": {"c_jr"},
     "c_jalr": {"c_ebreak"},
     "c_add": {"c_ebreak", "c_jalr"},
+    "yadd": {"ymv"},
+    "ymodew": {"ymodeswy", "ymodeswi"},
 }
 
 isa_regex = re.compile(
@@ -103,6 +108,7 @@ def read_arg_lut_csv(filename: str) -> "dict[str, tuple[int, int]]":
     "imm12lo": "imm[4:0]",
     "jimm20": "imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]",
     "zimm": "uimm",
+    "ybndswimm9": "uimm[8:0]",
     "shamtw": "shamt",
     "shamtd": "shamt",
     "shamtq": "shamt",
@@ -115,6 +121,7 @@ def read_arg_lut_csv(filename: str) -> "dict[str, tuple[int, int]]":
     "c_rs2_n0": "rs2$\\neq$0",
     "rd_n0": "rd$\\neq$0",
     "rs1_n0": "rs1$\\neq$0",
+    "rs2_n0": "rs2$\\neq$0",
     "c_rs1_n0": "rs1$\\neq$0",
     "rd_rs1": "rd/rs1",
     "zimm6hi": "uimm[5]",