Search results

Hello everyone! I’m just starting 😉

Status: Open.

#56 In sgherbst/anasymod;

· bassTon05 opened on May 18, 2024

Delete unused buildkite pipeline/webhook

Status: Open.

#55 In sgherbst/anasymod;

· steveri opened on Apr 9, 2024

Add support for using SymbiFlow open source tooling instead of Vivado

Status: Open.

#54 In sgherbst/anasymod;

· mithro opened on Aug 4, 2021

Consider using edalize to drive EDA tooling

Status: Open.

#53 In sgherbst/anasymod;

· mithro opened on Aug 4, 2021

Add method to auto-populate sim_ctrl.sv I/Os and initialization

Status: Open.

#51 In sgherbst/anasymod;

· sgherbst opened on Jul 13, 2021

Add semi-custom firmware option

Status: Open.

#50 In sgherbst/anasymod;

· sgherbst opened on Jul 13, 2021

Provide method to add user-defined synthesis/implementation constraints

Status: Open.

#49 In sgherbst/anasymod;

· sgherbst opened on Jul 13, 2021

Provide method to get UART port / PySerial object without programming FPGA

Status: Open.

#48 In sgherbst/anasymod;

· sgherbst opened on Jun 5, 2021

Provide method to adjust synthesis and implementation effort

Status: Open.

#47 In sgherbst/anasymod;

· sgherbst opened on Jun 5, 2021

Provide method to treat *.v files as SystemVerilog files in Vivado

Status: Open.

#43 In sgherbst/anasymod;

· sgherbst opened on Jan 28, 2021

Use tree structure to take the minimum of timestep requests

Status: Open.

#35 In sgherbst/anasymod;

· sgherbst opened on Aug 23, 2020

Make it harder to accidentally delete bitfiles

Status: Open.

#34 In sgherbst/anasymod;

· sgherbst opened on Aug 14, 2020