riscv: gate D-width atomic translators on the A extension

[carlosqwqqwq]

Fixes #2389

Problem

The eleven RV64 D-width atomic translators in trans_rva.inc.c (trans_lr_d, trans_sc_d, trans_amoswap_d, trans_amoadd_d, trans_amoxor_d, trans_amoand_d, trans_amoor_d, trans_amomin_d, trans_amomax_d, trans_amominu_d, trans_amomaxu_d) emit their memory operations without the REQUIRE_EXT(ctx, RVA) check that every W-width sibling performs, so they retire and modify memory on harts without A instead of raising an illegal-instruction exception.

Change

Add REQUIRE_EXT(ctx, RVA); as the first statement of each of the eleven D-width translators. The check traps at the first D-width atomic before any memory effect, matching the W-width translators and upstream QEMU. The focused unit test is test_riscv64_dwidth_atomic_without_a in tests/unit/test_riscv.c.

Validation

• Rebased onto dev and built the RISC-V targets.
• The public u030 suite includes the A-clear profile patch, a D-width witness, and a W-width control.
• The D-width witness traps on the A-clear profile; the W-width control retains its existing behavior.

Public reproducer and explicit profile setup:
https://github.com/carlosqwqqwq/unicorn-riscv-repros/tree/main/u030

[carlosqwqqwq]

Thank you very much for taking the time to review this PR. We have rebased it onto dev and applied the extension check consistently to the D-width atomic translators, with focused validation of the affected behavior. Could you please let us know what further code, test, or PR changes you would recommend? We will gladly adjust the patch to match the project guidelines.