RISC-V: add optional architectural trap entry

[Kreijstal]

RISC-V exceptions currently call UC_HOOK_INTR and advance pc without updating the trap CSRs or jumping to mtvec.

This adds an opt-in control:

uc_ctl_set_architectural_exceptions(uc, true);

When enabled on RISC-V, cpu_handle_exception() calls QEMU's existing riscv_cpu_do_interrupt() before invoking UC_HOOK_INTR. The hook receives the original exception number.

The option is disabled by default, so existing RISC-V behavior does not change. Other architectures return UC_ERR_ARCH when the control is used.

The new unit test checks that an M-mode ecall sets pc, mepc, mcause, and the privilege mode. The existing ecall test still checks the default PC-advance behavior.

Fixes #2402

[wtdcode]

This looks good, but honestly, the uc_ctl does not seem like the correct place. What's your use case?

[Kreijstal]

This looks good, but honestly, the uc_ctl does not seem like the correct place. What's your use case?

trying to emulate full-system riscv32 firmware, It simulates SiFive HiFive1 Rev B development board, using the SiFive FE310.

QEMU cannot do this, so I thought I could it it with unicorn.

[wtdcode]

This looks good, but honestly, the uc_ctl does not seem like the correct place. What's your use case?

trying to emulate full-system riscv32 firmware, It simulates SiFive HiFive1 Rev B development board, using the SiFive FE310.

QEMU cannot do this, so I thought I could it it with unicorn.

Sorry I mean why it should not advance PC?

[Kreijstal]

"When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was
interrupted or that encountered the exception." page 49 https://docs.riscv.org/reference/isa/_attachments/riscv-privileged.pdf

so the +4 happens in the m trap handler which happens on the firmware

unicorn assumes you have no firmware, so it does it for you, but if you want to emulate the firmware, unicorn should allow you to do the +4 (in the firmware), or more strictly I want to model m-trap handling in riscv itself