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[Misc] Define HiSparse source readiness interface - #3

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[Misc] Define HiSparse source readiness interface#3
LifeOfCoffee wants to merge 124 commits into
zhenwenqi2024:feat/hisparse-foundation-20261104from
LifeOfCoffee:codex/hisparse-source-ready-contract

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@LifeOfCoffee LifeOfCoffee commented Nov 12, 2026

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What this PR does / why we need it?

Define the minimal worker-side HiSparseSourceReady Protocol for a follow-up HiSparse + AscendStore pooling implementation. The contract waits for requested Host/Source blocks to complete writeback and raises when they have been canceled or invalidated.

This PR is stacked on vllm-ascend PR vllm-project#20926. It intentionally does not wire the Protocol into the scheduler or Memcache backend and does not change runtime behavior.

Does this PR introduce any user-facing change?

No. This is an internal type-only interface definition.

How was this patch tested?

  • python -m py_compile vllm_ascend/distributed/kv_transfer/kv_pool/ascend_store/metadata.py — passed.
  • ruff check vllm_ascend/distributed/kv_transfer/kv_pool/ascend_store/metadata.py — passed.
  • ruff format --check vllm_ascend/distributed/kv_transfer/kv_pool/ascend_store/metadata.py — passed.
  • git diff --check — passed.
  • bash format.sh ci — not completed locally: first-time pre-commit actionlint environment installation stalled. CI remains to run.
  • No NPU test is applicable to a Protocol declaration with no runtime consumer.

Checklist

  • The diff is limited to one internal Protocol declaration.
  • No runtime behavior or user-facing API changed.
  • Required CI checks pass before merge.

@zhenwenqi2024
feat(hisparse): add Ascend backend foundation
ca8744e 
Split the unquantized NPU data path from PR19109 onto current Ascend main. Reuse merged Core backend, HMA, Coordinator and lifetime interfaces, expose device cache operations and view hooks, and document independent contribution areas. Exclude C8 tuning, P/D transport, native optimized kernels and experiment profiles.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
docs(hisparse): add foundation release note
5c1ed89 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): reuse Core generic stream and event APIs
8a20e1c 
Remove the module-local Torch facade and its native stream/context wrappers. Preserve Core event placement and add a changing-graph fork/join regression with CANN allocation. Generic/native component comparisons and extracted merged-Core stream methods passed on Ascend 950; complete package and model qualification remain pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): pass index groups through Core MLA modules
c500c53 
Use MLAModules.index_group_builder for the model-owned group builder and remove the extra Ascend wrapper keyword. Preserve existing checkpoint, DCP, PP and post-load behavior. Source-isolated checks use actual merged Core modules/group builders and both constructor bodies; 16 configurations and 26 CPU regressions pass. This is not NPU or full-model qualification.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): trim compatibility adapters and consolidate tests
e2f0e2d 
Reuse main explicit-dtype weight loading and Core private Host-pool defaults. Keep the necessary Core coordinator, shared-budget and view bridges. Remove synthetic loader/signature checks, consolidate capture and ordering coverage, and exercise real CPU workspace ownership. Sixteen CPU cases pass and all forty declared NPU combinations remain; full device/model qualification and full CI are still pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
feat(hisparse): restore native C8 foundation
153497b 
Reuse native SFA quantization and Attention, byte-capable scatter, and Core HMA/lifecycle ownership. Bind packed main rows and page-strided Indexer keys/scales without optional optimization profiles.

Add payload, addressing, alignment and eager/Graph regression coverage. Source-isolated CPU checks pass (23 cases); new-head NPU and full-model qualification remain pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): narrow foundation coverage to Ascend adapters
b3a6bf2 
Remove the embedded activation dump, generic stream probe, duplicate prefill and order checks, and mock-only Core forwarding tests. Reuse existing SFA preprocessing as the reference for one BF16/C8 destination test.

Retain device resolver/refill/invalidation, packed layouts and graph coverage. Production code and Attention kernels are unchanged. Twenty source-isolated CPU cases pass; NPU qualification remains pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): scope FP8 platform guard to C8 attention
139fb5f 
Allow the BF16 bridge test to use the native SFA registration on A2, A3 and A5. Keep only the native E4M3FN C8 case restricted to A5 and skip the unregistered 310P operation. No production or kernel changes.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): import production modules directly in UT
4524027 
Remove AST extraction, dynamic exec/file loading and replacement base/spec classes. Exercise the actual backend inheritance, Core/Ascend cache specs and metadata builder through normal imports and the existing CPU-UT conftest.

Keep the same twenty boundary cases. Standard pytest was attempted but collection is blocked by missing local vllm dependencies; no source-isolated pass is claimed for this version. Focused syntax, Ruff, Markdown and diff checks pass.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): select Indexer writes through the backend
fa9704a 
Use a HiSparse Indexer subclass and the existing write_cache override. Restore ordinary Indexer write/build behavior and remove payload-format attributes and string routing. Reuse the cache backend choice in the model wrapper while retaining model-specific factories.

Keep the existing C8 stride helpers and native kernels unchanged. Update existing writer/wrapper tests; standard UT collection remains blocked by missing local vllm. Focused checks pass; full lint failed installing actionlint after a remote disconnect.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): group shared cache code and own Attention dispatch
b22942d 
Place backend, binding, cache operations and C8 layout helpers in vllm_ascend/hisparse. Move the C8 native Attention invocation into AscendHiSparseImpl, which already owns its length workspace. Update the platform path and all consumers without compatibility forwarding modules.

Keep data transformations, allocator behavior, kernel arguments and native/Triton kernels unchanged. Existing C8 device coverage now enters the Attention backend. Packaging, syntax, focused lint and structural equivalence checks pass; standard UT and full lint remain blocked by local dependencies/tool installation.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): record device qualification and fix scatter reference
5bdb93a 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): preserve prefill row mapping on NPU
2b66c7b 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): retain indexer backend beyond model construction
e282c9c 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): preserve core indexer cache roles and layout
83e4655 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): allocate pinned private pools before cache views
81100e0 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): propagate captured side-stream waits before workspace …
8042477 
…allocation

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): adapt the bound runtime stream before graph capture
0267e49 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
docs(hisparse): record full-model foundation qualification
908bc2c 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): use the fused native residency resolver
6ea9e78 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): integrate resolver with AscendC operator build
a1dc5e6 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): retain mixed AscendC SIMT compilation mode
5934d4a 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): preserve copy stream during graph capture
056aa91 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
perf(hisparse): reuse native C8 Prolog with owned staging
37a42a2 
Keep Core lifecycle and Resident row mapping. Qualify this private candidate on NPU before publishing any performance claim.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): match native C8 Prolog MXFP8 contract
5b786fc 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
perf(hisparse): consume native compact C8 indices in Attention
e954dcf 
Keep virtual refill rows separate and qualify bound HMA geometry. Leave Prefill mapping unchanged. Private candidate pending actual NPU and model qualification.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): retain native fallback for INT8 projection weights
172d382 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): initialize native ops for focused NPU selections
1be712f 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): declare dtype in workspace ownership fixture
66e11b5 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
docs(hisparse): record current native C8 qualification and limits
fc39fa8 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
zhenwenqi2024 and others added 28 commits November 11, 2026 11:14
@zhenwenqi2024
refactor(hisparse): install row adapters without source hashes
3f48a57 
Use the existing binding and transfer lifecycle directly. Remove whole-file source allowlists and the optional recycled-adapter installation path.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): collapse the native resolver forwarding helper
383ba6b 
Call the native resolver directly from the existing owner-aware dispatch entry. Preserve all native arguments and runtime-owned scratch views.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): use Core copy streams directly
b22dbf6 
Remove the capture-only stream wrapper after validating the fused resolver and refill with generic torch.Stream on Ascend950. Both wrapped and generic cross-stream cases pass, and the removal passes six resolver/refill and workspace rebind Graph cases.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
perf(hisparse): generalize sorted slot invalidation
f1007cd 
Choose sorted invalidation from the table and write geometry, with a bounded sort buffer. Use the same selection during graph capture and verify changing writes on both single-stream and cross-stream replay.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): share native resolver UB budget checks
ec9338e 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): reuse SFA KV preprocessing
068ed15 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): keep RoPE sharing out of the foundation
78ab285 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
chore(hisparse): drop unrelated model-state formatting
7792381 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): simplify Prefill staging and Indexer validation
56ec033 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): consolidate resolver dispatch and SFA tests
554334c 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): consolidate Prefill and Host allocation ownership
72218c9 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): reuse Core row DMA descriptor construction
fea0b75 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
refactor(hisparse): consolidate worker DMA hooks into backend
aed45ce 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
chore(hisparse): merge upstream main for PR validation
d2c5dbb 
Preserve the upstream Indexer metadata and PCP behavior alongside HiSparse physical page mapping and cache-role tests.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): use real attention defaults in worker fixtures
c4d8bc9 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
chore(hisparse): preserve the latest PR updates in CI fix
9a99d64 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): cover the native miss loop and supported Core interface
29e6b32 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): use the shared vLLM logger
8cf106d 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): follow the current indexer and metadata contracts
9cd801d 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): type the cache layout and verification paths
08aacc7 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): initialize SFA flags in device fixtures
58f9578 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(hisparse): bind C8 indexer views from the full Core page
b1920e7 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): exercise the Core page view on NPU
4c813f2 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(ci): reuse sources that already include the base snapshot
8c2cc01 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): register device suite durations for CI selection
b6a87be 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
test(hisparse): use real attention defaults in the remaining CPU fixt…
1d3d791 
…ures

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@zhenwenqi2024
fix(ci): preserve the based snapshot in csrc cache checks
48e4b4a 
Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>
@LifeOfCoffee
chore: define HiSparse source readiness interface
f8110b0 
Add the minimal worker-side Host writeback contract for the follow-up AscendStore pooling integration. This commit does not wire or change runtime behavior.

Signed-off-by: LifeOfCoffee <lcyzhyx@163.com>
@weiguihua2
weiguihua2 force-pushed the feat/hisparse-foundation-20261104 branch from c3c593c to d47fa42 Compare November 12, 2026 07:36
@zhenwenqi2024
zhenwenqi2024 force-pushed the feat/hisparse-foundation-20261104 branch from 3854bfd to b77ec2e Compare November 12, 2026 13:29
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@LifeOfCoffee @zhenwenqi2024