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ca8744e
feat(hisparse): add Ascend backend foundation
zhenwenqi2024 Nov 4, 2026
5c1ed89
docs(hisparse): add foundation release note
zhenwenqi2024 Nov 4, 2026
8a20e1c
refactor(hisparse): reuse Core generic stream and event APIs
zhenwenqi2024 Nov 4, 2026
c500c53
refactor(hisparse): pass index groups through Core MLA modules
zhenwenqi2024 Nov 4, 2026
e2f0e2d
refactor(hisparse): trim compatibility adapters and consolidate tests
zhenwenqi2024 Nov 4, 2026
153497b
feat(hisparse): restore native C8 foundation
zhenwenqi2024 Nov 4, 2026
b3a6bf2
test(hisparse): narrow foundation coverage to Ascend adapters
zhenwenqi2024 Nov 4, 2026
139fb5f
test(hisparse): scope FP8 platform guard to C8 attention
zhenwenqi2024 Nov 4, 2026
4524027
test(hisparse): import production modules directly in UT
zhenwenqi2024 Nov 4, 2026
fa9704a
refactor(hisparse): select Indexer writes through the backend
zhenwenqi2024 Nov 4, 2026
b22942d
refactor(hisparse): group shared cache code and own Attention dispatch
zhenwenqi2024 Nov 4, 2026
5bdb93a
test(hisparse): record device qualification and fix scatter reference
zhenwenqi2024 Nov 4, 2026
2b66c7b
fix(hisparse): preserve prefill row mapping on NPU
zhenwenqi2024 Nov 4, 2026
e282c9c
fix(hisparse): retain indexer backend beyond model construction
zhenwenqi2024 Nov 4, 2026
83e4655
fix(hisparse): preserve core indexer cache roles and layout
zhenwenqi2024 Nov 4, 2026
81100e0
fix(hisparse): allocate pinned private pools before cache views
zhenwenqi2024 Nov 4, 2026
8042477
fix(hisparse): propagate captured side-stream waits before workspace …
zhenwenqi2024 Nov 4, 2026
0267e49
fix(hisparse): adapt the bound runtime stream before graph capture
zhenwenqi2024 Nov 4, 2026
908bc2c
docs(hisparse): record full-model foundation qualification
zhenwenqi2024 Nov 4, 2026
6ea9e78
refactor(hisparse): use the fused native residency resolver
zhenwenqi2024 Nov 5, 2026
a1dc5e6
refactor(hisparse): integrate resolver with AscendC operator build
zhenwenqi2024 Nov 5, 2026
5934d4a
fix(hisparse): retain mixed AscendC SIMT compilation mode
zhenwenqi2024 Nov 5, 2026
056aa91
test(hisparse): preserve copy stream during graph capture
zhenwenqi2024 Nov 5, 2026
37a42a2
perf(hisparse): reuse native C8 Prolog with owned staging
zhenwenqi2024 Nov 5, 2026
5b786fc
test(hisparse): match native C8 Prolog MXFP8 contract
zhenwenqi2024 Nov 5, 2026
e954dcf
perf(hisparse): consume native compact C8 indices in Attention
zhenwenqi2024 Nov 5, 2026
172d382
fix(hisparse): retain native fallback for INT8 projection weights
zhenwenqi2024 Nov 5, 2026
1be712f
test(hisparse): initialize native ops for focused NPU selections
zhenwenqi2024 Nov 5, 2026
66e11b5
test(hisparse): declare dtype in workspace ownership fixture
zhenwenqi2024 Nov 5, 2026
fc39fa8
docs(hisparse): record current native C8 qualification and limits
zhenwenqi2024 Nov 5, 2026
26c0252
perf(hisparse): reuse resolver counts for C8 empty-row masking
zhenwenqi2024 Nov 5, 2026
a596bbf
perf(hisparse): prepare immutable C8 decode lengths at binding
zhenwenqi2024 Nov 5, 2026
6e4e251
perf(hisparse): reuse native C8 empty-query output handling
zhenwenqi2024 Nov 5, 2026
5264744
docs(hisparse): record native C8 output qualification and remaining r…
zhenwenqi2024 Nov 5, 2026
1861b61
perf(hisparse): bound compact refill programs for current miss counts
zhenwenqi2024 Nov 5, 2026
03cc8b3
refactor(hisparse): omit unused C8 softmax LSE outputs
zhenwenqi2024 Nov 5, 2026
0f158d9
refactor(hisparse): reuse Core device request mapping
zhenwenqi2024 Nov 5, 2026
7fa1df0
perf(hisparse): reuse indexer store with page strides
zhenwenqi2024 Nov 5, 2026
5a45320
fix(hisparse): preserve indexer scale payload bits
zhenwenqi2024 Nov 5, 2026
1efad34
fix(indexer): derive contiguous page-stride defaults
zhenwenqi2024 Nov 5, 2026
6ef170d
test(hisparse): mock the shared indexer store boundary on CPU
zhenwenqi2024 Nov 5, 2026
fcdeef2
perf(hisparse): reuse PTA queue for small host mirror submissions
zhenwenqi2024 Nov 6, 2026
b2dfb24
docs(hisparse): record matched zero-miss qualification
zhenwenqi2024 Nov 6, 2026
ca2212f
perf(hisparse): prototype Target mirror overlap with MTP
zhenwenqi2024 Nov 6, 2026
7bc7b5d
perf(hisparse): batch row mirror DMA descriptor preparation
zhenwenqi2024 Nov 6, 2026
d9e19fc
perf(hisparse): overlap Host mirror with Target sampling
zhenwenqi2024 Nov 6, 2026
42b3aef
perf(hisparse): stage Target rows before overlapping draft
zhenwenqi2024 Nov 6, 2026
23949ef
perf(hisparse): reuse Target RoPE metadata within decode forwards
zhenwenqi2024 Nov 6, 2026
42ce764
perf(hisparse): write Target Prolog C8 rows directly to Resident
zhenwenqi2024 Nov 6, 2026
a47cbfd
perf(hisparse): prefetch shared-indexer followers for C8 MTP Target
zhenwenqi2024 Nov 6, 2026
0a9b0e4
refactor(hisparse): remove unused scalar compact refill branch
zhenwenqi2024 Nov 6, 2026
51e61b5
perf(hisparse): prefetch every shared compact swap plan
zhenwenqi2024 Nov 6, 2026
d3096a1
perf(hisparse): overlap prefill Host misses across shared-indexer layers
zhenwenqi2024 Nov 6, 2026
a20218c
fix(hisparse): bound Prefill Resident gather byte tile
zhenwenqi2024 Nov 6, 2026
4c0ef30
perf(hisparse): group recycled Host block invalidation
zhenwenqi2024 Nov 6, 2026
1e50646
perf(hisparse): group all valid recycled Host blocks
zhenwenqi2024 Nov 6, 2026
0fcbdd5
refactor(hisparse): reuse Core speculative group prefetch
zhenwenqi2024 Nov 6, 2026
b494a3c
fix(mla): accept Core no-argument post-load hook
zhenwenqi2024 Nov 6, 2026
f6393dd
fix(worker): accept Core KV allocation callback ABI
zhenwenqi2024 Nov 6, 2026
c67eb79
perf(hisparse): read resident pages in eager C8 prefill
zhenwenqi2024 Nov 6, 2026
bf872fc
perf(hisparse): simplify contiguous C8 row mapping
zhenwenqi2024 Nov 6, 2026
b5f75fa
perf(hisparse): use resident pages for mixed-batch prefill
zhenwenqi2024 Nov 6, 2026
f5d96c8
test(hisparse): report resident prefill activation per worker
zhenwenqi2024 Nov 6, 2026
dbdec2d
perf(hisparse): bound large written-slot invalidation
zhenwenqi2024 Nov 6, 2026
0d07bd6
fix(hisparse): bound Ascend device-to-host DMA batches
zhenwenqi2024 Nov 6, 2026
b94775b
chore(hisparse): integrate Ascend main into foundation
zhenwenqi2024 Nov 7, 2026
3d5c9d6
chore(hisparse): sync upstream test cleanup
zhenwenqi2024 Nov 7, 2026
b86fdc4
perf(hisparse): align cold slot staging with Ascend producer dtype
zhenwenqi2024 Nov 7, 2026
8172616
chore(hisparse): trim stale qualification notes and test diagnostics
zhenwenqi2024 Nov 7, 2026
7a6e326
test(hisparse): remove duplicated scratch arithmetic assertions
zhenwenqi2024 Nov 8, 2026
114ab3e
test(hisparse): bootstrap SFA ops before device initialization
zhenwenqi2024 Nov 8, 2026
47a8276
perf(hisparse): size resolved-row scratch by configured TopK
zhenwenqi2024 Nov 8, 2026
251f0d9
test(hisparse): route device coverage to A5 and refresh fixtures
zhenwenqi2024 Nov 9, 2026
5a02c50
perf(hisparse): pass Resident staging extents at runtime
zhenwenqi2024 Nov 9, 2026
e661dc8
refactor(hisparse): trim redundant state and tests
zhenwenqi2024 Nov 9, 2026
c81a48f
perf(hisparse): reuse target logits index output workspace
zhenwenqi2024 Nov 9, 2026
5a54eb4
refactor(hisparse): trim dead scratch and duplicate test logic
zhenwenqi2024 Nov 9, 2026
ad32f84
test(hisparse): initialize shared TopK in rebind fixture
zhenwenqi2024 Nov 10, 2026
0271d60
refactor(hisparse): consolidate host storage and mirror ownership
zhenwenqi2024 Nov 10, 2026
32ae695
fix(hisparse): include binding workspaces in Core memory profiling
zhenwenqi2024 Nov 10, 2026
c366b41
fix(hisparse): allocate profiled workspaces outside inference mode
zhenwenqi2024 Nov 10, 2026
6bab22a
test(hisparse): cover profiled workspace owners and rebinds
zhenwenqi2024 Nov 10, 2026
29b9f33
refactor(worker): reuse Core token combination
zhenwenqi2024 Nov 10, 2026
7565876
refactor(hisparse): restore Core mirror completion flow
zhenwenqi2024 Nov 10, 2026
fd388b2
refactor(hisparse): write C8 Prolog output to the bound cache
zhenwenqi2024 Nov 10, 2026
a11b1b9
refactor(hisparse): prepare workspaces at worker startup
zhenwenqi2024 Nov 10, 2026
62d66e6
perf(attention): generalize SFA RoPE metadata reuse
zhenwenqi2024 Nov 10, 2026
52e6d78
perf(hisparse): reuse validity and clamped index intermediates
zhenwenqi2024 Nov 10, 2026
f414e7a
perf(hisparse): share the resident row-copy kernel
zhenwenqi2024 Nov 10, 2026
8d044bc
perf(hisparse): use column-first compact gather launches
zhenwenqi2024 Nov 10, 2026
aa7f5dd
fix(worker): preserve the metadata graph capture API
zhenwenqi2024 Nov 10, 2026
1f3b0d4
perf(hisparse): defer direct target mirror wait until after drafting
zhenwenqi2024 Nov 10, 2026
f4a1dbb
test(hisparse): cover direct Target mirror during Draft writes
zhenwenqi2024 Nov 10, 2026
fecc216
refactor(hisparse): keep the mirror join at the sample return
zhenwenqi2024 Nov 11, 2026
5e64181
refactor(hisparse): narrow runner host mirror hooks
zhenwenqi2024 Nov 11, 2026
822b6c3
refactor(hisparse): use Core grouped invalidation interface
zhenwenqi2024 Nov 11, 2026
3f48a57
refactor(hisparse): install row adapters without source hashes
zhenwenqi2024 Nov 11, 2026
383ba6b
refactor(hisparse): collapse the native resolver forwarding helper
zhenwenqi2024 Nov 11, 2026
b22dbf6
refactor(hisparse): use Core copy streams directly
zhenwenqi2024 Nov 11, 2026
f1007cd
perf(hisparse): generalize sorted slot invalidation
zhenwenqi2024 Nov 11, 2026
ec9338e
refactor(hisparse): share native resolver UB budget checks
zhenwenqi2024 Nov 11, 2026
068ed15
refactor(hisparse): reuse SFA KV preprocessing
zhenwenqi2024 Nov 11, 2026
78ab285
refactor(hisparse): keep RoPE sharing out of the foundation
zhenwenqi2024 Nov 11, 2026
7792381
chore(hisparse): drop unrelated model-state formatting
zhenwenqi2024 Nov 11, 2026
56ec033
refactor(hisparse): simplify Prefill staging and Indexer validation
zhenwenqi2024 Nov 11, 2026
554334c
refactor(hisparse): consolidate resolver dispatch and SFA tests
zhenwenqi2024 Nov 11, 2026
72218c9
refactor(hisparse): consolidate Prefill and Host allocation ownership
zhenwenqi2024 Nov 11, 2026
fea0b75
refactor(hisparse): reuse Core row DMA descriptor construction
zhenwenqi2024 Nov 11, 2026
aed45ce
refactor(hisparse): consolidate worker DMA hooks into backend
zhenwenqi2024 Nov 11, 2026
d2c5dbb
chore(hisparse): merge upstream main for PR validation
zhenwenqi2024 Nov 11, 2026
c4d8bc9
test(hisparse): use real attention defaults in worker fixtures
zhenwenqi2024 Nov 11, 2026
9a99d64
chore(hisparse): preserve the latest PR updates in CI fix
zhenwenqi2024 Nov 11, 2026
29e6b32
test(hisparse): cover the native miss loop and supported Core interface
zhenwenqi2024 Nov 11, 2026
8cf106d
fix(hisparse): use the shared vLLM logger
zhenwenqi2024 Nov 11, 2026
9cd801d
fix(hisparse): follow the current indexer and metadata contracts
zhenwenqi2024 Nov 11, 2026
08aacc7
fix(hisparse): type the cache layout and verification paths
zhenwenqi2024 Nov 11, 2026
58f9578
test(hisparse): initialize SFA flags in device fixtures
zhenwenqi2024 Nov 11, 2026
b1920e7
fix(hisparse): bind C8 indexer views from the full Core page
zhenwenqi2024 Nov 11, 2026
4c813f2
test(hisparse): exercise the Core page view on NPU
zhenwenqi2024 Nov 11, 2026
8c2cc01
fix(ci): reuse sources that already include the base snapshot
zhenwenqi2024 Nov 11, 2026
b6a87be
test(hisparse): register device suite durations for CI selection
zhenwenqi2024 Nov 11, 2026
1d3d791
test(hisparse): use real attention defaults in the remaining CPU fixt…
zhenwenqi2024 Nov 11, 2026
48e4b4a
fix(ci): preserve the based snapshot in csrc cache checks
zhenwenqi2024 Nov 11, 2026
f8110b0
chore: define HiSparse source readiness interface
LifeOfCoffee Nov 12, 2026
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2 changes: 1 addition & 1 deletion .github/workflows/_build_csrc_cache.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -152,7 +152,7 @@ jobs:
fi
git fetch "$BASE_REMOTE" "$BASE_REF"
git cat-file -e "${BASE_SHA}^{commit}"
git rebase "$BASE_SHA"
git merge-base --is-ancestor "$BASE_SHA" HEAD || git rebase "$BASE_SHA"

- name: Update submodules
run: |
Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/_ensure_csrc_cache.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ jobs:
fi
git fetch "$BASE_REMOTE" "$BASE_REF"
git cat-file -e "${BASE_SHA}^{commit}"
git rebase "$BASE_SHA"
git merge-base --is-ancestor "$BASE_SHA" HEAD || git rebase "$BASE_SHA"

- name: Calculate csrc hash
id: hash
Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/_selected_tests.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -161,7 +161,7 @@ jobs:
BASE_SHA=$(git rev-parse FETCH_HEAD)
fi
git cat-file -e "${BASE_SHA}^{commit}"
git rebase "$BASE_SHA"
git merge-base --is-ancestor "$BASE_SHA" HEAD || git rebase "$BASE_SHA"
git submodule sync --recursive
git submodule update --init --recursive

Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/_selected_tests_upstream.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -146,7 +146,7 @@ jobs:
BASE_SHA=$(git rev-parse FETCH_HEAD)
fi
git cat-file -e "${BASE_SHA}^{commit}"
git rebase "$BASE_SHA"
git merge-base --is-ancestor "$BASE_SHA" HEAD || git rebase "$BASE_SHA"
git submodule sync --recursive
git submodule update --init --recursive

Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/pr_test.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -531,7 +531,7 @@ jobs:
exit 1
fi

git rebase "$BASE_SHA"
git merge-base --is-ancestor "$BASE_SHA" HEAD || git rebase "$BASE_SHA"
echo "base_sha=$BASE_SHA" >> "$GITHUB_OUTPUT"

- name: Validate test coverage config
Expand Down
3 changes: 3 additions & 0 deletions .github/workflows/scripts/estimated_times.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,9 @@ estimated_times:
tests/e2e/pull_request/one_card/test_kv_pool_accuracy.py: 410
tests/e2e/pull_request/one_card/test_flash_attn_precision.py: 30
tests/e2e/pull_request/one_card/test_swiglu_mx_quant.py: 30
tests/e2e/pull_request/one_card/test_hisparse_attention.py: 30
tests/e2e/pull_request/one_card/test_hisparse_ops.py: 30
tests/e2e/pull_request/one_card/test_hisparse_prefill_staging.py: 30
tests/e2e/pull_request/four_card/model_runner_v2/test_kvpp_pp.py: 300
tests/e2e/pull_request/four_card/test_kvpp_pd.py: 230
tests/e2e/pull_request/two_card/test_kvpp.py: 290
Expand Down
5 changes: 5 additions & 0 deletions .github/workflows/scripts/test_config.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,9 @@ curated_tests:
- tests/e2e/pull_request/one_card/test_mla_fp8_decode_layout_a5.py
- tests/e2e/pull_request/one_card/test_flash_attn_precision.py
- tests/e2e/pull_request/one_card/test_swiglu_mx_quant.py
- tests/e2e/pull_request/one_card/test_hisparse_attention.py
- tests/e2e/pull_request/one_card/test_hisparse_ops.py
- tests/e2e/pull_request/one_card/test_hisparse_prefill_staging.py

# === Skipped Tests ===
# Removed from any selection after directory scanning, so they are never
Expand Down Expand Up @@ -119,6 +122,8 @@ runner_mapping:
default: a5-4
tests/e2e/pull_request/one_card/test_swiglu_mx_quant\.py$:
default: a5-4
tests/e2e/pull_request/one_card/test_hisparse_(attention|ops|prefill_staging)\.py$:
default: a5-4
tests/e2e/pull_request/one_card:
default: a2-1
310p: 310p-1
Expand Down
15 changes: 15 additions & 0 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -232,3 +232,18 @@ if(SOC_VERSION MATCHES "ascend310p.*|ascend950")
else()
install(TARGETS vllm_ascend_C vllm_ascend_kernels DESTINATION ${VLLM_ASCEND_INSTALL_PATH})
endif()

# SIMT HiSparse kernels use CANN's ASC CMake language integration. Other SOCs
# retain their existing build and report HiSparse unavailable when selected.
if(SOC_VERSION MATCHES "ascend950")
find_path(HISPARSE_SIMT_INCLUDE_DIR simt_api/asc_simt.h
PATHS
${ASCEND_HOME_PATH}/asc/include
${ASCEND_HOME_PATH}/${CMAKE_SYSTEM_PROCESSOR}-linux/asc/include
NO_DEFAULT_PATH)
if(HISPARSE_SIMT_INCLUDE_DIR)
add_subdirectory(csrc/hisparse)
target_compile_definitions(vllm_ascend_C PRIVATE VLLM_ASCEND_ENABLE_HISPARSE_RESOLVER)
target_link_libraries(vllm_ascend_C PRIVATE vllm_ascend_hisparse)
endif()
endif()
16 changes: 16 additions & 0 deletions csrc/hisparse/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
# SPDX-License-Identifier: Apache-2.0
# CANN's ASC integration supplies the compiler, archive rules and runtime links.
find_package(ASC REQUIRED CONFIG PATHS
${ASCEND_HOME_PATH}/lib64/cmake
${ASCEND_HOME_PATH}/${CMAKE_SYSTEM_PROCESSOR}-linux/lib64/cmake
NO_DEFAULT_PATH)
set(CMAKE_ASC_ARCHITECTURES dav-3510)
enable_language(ASC)

ascendc_library(vllm_ascend_hisparse STATIC hisparse_resolver.cpp)
target_include_directories(vllm_ascend_hisparse PRIVATE ${HISPARSE_SIMT_INCLUDE_DIR})
# The AscendC entry launches a SIMT vector function through asc_vf_call. Keep
# the mixed programming mode; --enable-simt selects a pure SIMT translation unit.
target_compile_options(vllm_ascend_hisparse PRIVATE -O2)
# Reserve space for the descriptor and runtime overhead within the target UB.
target_compile_definitions(vllm_ascend_hisparse PRIVATE HISPARSE_RESOLVER_UB_BYTES=175616)
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