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AXI DMA 1 MiB transfer limit blocks AES-GCM encrypt/decrypt of payloads larger than 1 MiB #1347

Description

@RaunakGu

Description

The AXI DMA controller caps a single transfer at 1 MiB (DMA_MAX_XFER_SIZE in axi_dma_ctrl.sv); larger transfers are rejected by the command-parse check before any data moves.

For SHA, firmware works around this by chunking the data into multiple ≤ 1 MiB DMA transfers — the SHA accelerator accumulates across transfers, so the digest is unaffected (see chipsalliance/caliptra-sw#3940).

For AES-GCM, that workaround does not apply. Each AES-GCM DMA transfer is a self-contained GCM_TEXT operation, so simply splitting a payload across transfers corrupts the GHASH state and produces a wrong authentication tag. There is currently no supported way to chunk AES-GCM over DMA.

The practical consequence is that AES-GCM encrypt/decrypt of payloads larger than 1 MiB is not supported over the DMA path.

Question

Is there a plan to address this in an upcoming RTL milestone — either by raising the DMA transfer-size limit, or by providing a supported multi-transfer GCM streaming mode so that AES-GCM can process payloads larger than 1 MiB?

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