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[DOC] Entropy source block diagram does not match RTL

Status: Open.

#1368 In chipsalliance/caliptra-rtl;

· ravithakurAMD opened on Aug 12, 2026

How can sha3_ctrl process messages that are not a multiple of 4 bytes long?

2.2

Status: Open.

#1361 In chipsalliance/caliptra-rtl;

· rswarbrick opened on Aug 4, 2026

Firmware make flow silently links a stale caliptra_isr.o from a previously built test when tests are built sequentially in one build directory (livelock in smoke_test_mldsa_externalmu)

Status: Open.

#1360 In chipsalliance/caliptra-rtl;

· li3tuo4 opened on Aug 3, 2026

Remove SHA AXI access when in passive mode

2.2

Status: Open.

Task

#1359 In chipsalliance/caliptra-rtl;

· clayton8 opened on Jul 31, 2026

·  

2.2 Core RTL

[DOC] Update tieoff recommendation for strap_ss_caliptra_dma_axi_user in passive mode

2.0

2.1

documentationImprovements or additions to documentationImprovements or additions to documentation

Status: Open.

Task

#1358 In chipsalliance/caliptra-rtl;

· clayton8 opened on Jul 31, 2026

[Question] abr_prim_generic handling

Status: Open.

#1355 In chipsalliance/caliptra-rtl;

· jchanga opened on Jul 31, 2026

[Question] The time for asserting scan_mode before scan is enabled

Status: Open.

#1354 In chipsalliance/caliptra-rtl;

· jchanga opened on Jul 31, 2026

AXI DMA 1 MiB transfer limit blocks AES-GCM encrypt/decrypt of payloads larger than 1 MiB

Future

Status: Open.

#1347 In chipsalliance/caliptra-rtl;

· RaunakGu opened on Jul 17, 2026

[sha3_ctrl,doc] It is impossible to run cSHAKE with empty N and S

2.2

documentationImprovements or additions to documentationImprovements or additions to documentation

Status: Open.

#1345 In chipsalliance/caliptra-rtl;

· rswarbrick opened on Jul 15, 2026

Need confirmation on Adams Bridge version for Caliptra 2.1.2

Status: Open.

#1343 In chipsalliance/caliptra-rtl;

· arm-caliptra opened on Jul 13, 2026

[dv] Port block-level design verification for csrng block.

Status: Open.

#1329 In chipsalliance/caliptra-rtl;

· moidx opened on Jul 2, 2026

·  

2.2 Core RTL

[dv] Port block-level design verification for entropy_src block.

Status: Open.

#1328 In chipsalliance/caliptra-rtl;

· moidx opened on Jul 2, 2026

·  

2.2 Core RTL