Add Supervisor Domains extension and CSRs - #389
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Signed-off-by: Ravi Sahita <ravi@rivosinc.com>
Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## master #389 +/- ##
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+ Coverage 96.53% 97.08% +0.55%
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Files 10 14 +4
Lines 750 926 +176
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+ Hits 724 899 +175
- Misses 26 27 +1 ☔ View full report in Codecov by Sentry. 🚀 New features to boost your workflow:
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| #define MIE_SSIE (1 << IRQ_S_SOFT) | ||
| #define MIE_VSSIE (1 << IRQ_VS_SOFT) | ||
| #define MIE_MSIE (1 << IRQ_M_SOFT) | ||
| #define MIE_STIE (1 << IRQ_S_TIMER) | ||
| #define MIE_VSTIE (1 << IRQ_VS_TIMER) | ||
| #define MIE_MTIE (1 << IRQ_M_TIMER) | ||
| #define MIE_SEIE (1 << IRQ_S_EXT) | ||
| #define MIE_VSEIE (1 << IRQ_VS_EXT) | ||
| #define MIE_MEIE (1 << IRQ_M_EXT) | ||
| #define MIE_SGEIE (1 << IRQ_S_GEXT) | ||
| #define MIE_LCOFIE (1 << IRQ_LCOF) | ||
| #define MIE_MSDEIE (1 << IRQ_MSDEI) | ||
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Let's get rid of this. It is a property of the ISA that MIP and MIE bits line up with each other, so having a redundant set of macros is just more code to maintain.
| #define SIP_STIP MIP_STIP | ||
| #define SIP_MSDEIP MIP_MSDEIP | ||
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| #define SIE_MSDEIE MIE_MSDEIE |
Andrew Waterman (aswaterman)
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Ved Shanbhogue (@ved-rivos) can you also take a quick look? Do you agree this is stable enough that it's safe to merge?
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Thanks Ravi Sahita (@rsahita)! |
Signed-off-by: Ravi Sahita <ravi@rivosinc.com>
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For the development of SMMTT support in Qemu and OpenSBI its imperative to have some confirmation on the proposed encodings of mfence/minval instructions and other CSRs and fields. Though riscv-smmtt spec is not yet frozen which may be gating this PR but please let us know if atleast SMSDID and SMMPT introduced instructions and CSRs encodings are good enough in the PR. |
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One of the spec authors will have to chime in and make sure that this PR matches the most recent version of the spec. |
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Ravi Sahita (@rsahita) Can you please confirm? |
Add Supervisor Domains extension and CSRs