Revert latch fix that causes Verilator failures

chipsalliance · Nov 11, 2024 · 16837fd · 16837fd
1 parent 53e9512
commit 16837fd
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
@@ -760,10 +760,16 @@ module `TEC_RV_ICG
 
    assign      enable = EN | SE;
 
+`ifdef VERILATOR
+   always @(negedge CK) begin
+      en_ff <= enable;
+   end
+`else
    always @(CK, enable) begin
       if(!CK)
         en_ff = enable;
    end
+`endif
    assign Q = CK & en_ff;
 
 endmodule