Skip to content
This repository was archived by the owner on Jul 17, 2026. It is now read-only.

Pull requests: riscv-collab/riscv-openocd

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort

Pull requests list

Add riscv as a zephyr target
#1315 opened Nov 17, 2025 by jdavidberger Loading…
target/riscv: fix ub during instruction decode
#1299 opened Oct 15, 2025 by aap-sc Loading…
fix error detection during trigger removal
#1296 opened Oct 7, 2025 by aap-sc Loading…
target/riscv: access registers via reg->type
#1269 opened Jun 20, 2025 by en-sc Collaborator Loading…
target/riscv: fix riscv_mmu behaviour
#1256 opened May 14, 2025 by fkhaidari Contributor Loading…
target/riscv: Adjust to upstream coding style
#1254 opened May 6, 2025 by berolinux Contributor Loading…
target/riscv: add is_virtual parameter to memory access method
#1241 opened Mar 18, 2025 by fkhaidari Contributor Loading…
enable additional platforms in CI
#1121 opened Aug 30, 2024 by aap-sc Loading…
Fix error on exit with uninitialized target
#1015 opened Feb 11, 2024 by tom-van Contributor Loading…
ProTip! no:milestone will show everything without a milestone.